Add support for Lenovo Thinkpad L520.
The files are generated by autoport,
and are successfully tested on the board.
L520 has got 4MiB flash chip, that contains a "slim" ME
with 1.2MiB only. The flash IC has to be desoldered, as
it won't be accessible in circuit. It is located on top
of the mainboard right under the touchpad.
Test-setup:
Extract the following blobs from vendor BIOS:
* Intel Flash Descriptor
* Intel Management Engine
* Intel VBios
The laptop has been externaly flashed. It was able to
turn on the display and load SeaBIOS.
Latest debian has been booted from harddisk.
Latest fedora has been booted from USB flash drive.
The following hardware has been tested and is working:
* Display using Option Rom
* PCIe wifi
* Ethernet
* Keyboard, trackpoint and touchpad
* Some Fn functions keys
* Volume Keys (except mic mute)
* Status LEDs
* Audio (headphone jack only)
* USB ports
* Native raminit dual channel (2 DDR3-1333 DIMMs tested)
* SATA cdrom
* SATA harddrive
Broken:
* Some Fn functions keys
* Microphone mute button
* Speakers (but headphone jack gives sound)
Untested:
* Expansion slot
* SD card slot
* Docking station
* Native gfx init
The EHCI debug port is the first one on the right side.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie7b248243339b52e6120c18ed217a740bc8992cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aae6e9cfe9
Original-Change-Id: Ic8943799b953bde09ff1daf8427ce5125a0778ca
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18003
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/431982
This fixes building coreboot with -std=gnu11 on gcc 4.9.x
Also needs fix ups for asus/kcma-d8 and asus/kgpe-d16 due to the missing
type.
BUG=none
BRANCH=none
TEST=none
Change-Id: I815127db725dd4bc3930e361d79d27a2a63eca80
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 06a629e4b1
Original-Change-Id: I920d492a1422433d7d4b4659b27f5a22914bc438
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18220
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/431985
This commit makes the initial changes to support the Intel Leaf Hill
CRB with Apollo Lake silicon. Memory parameters and some GPIOs are set.
The google/reef directory is used as a template, and the same IFWI
stitching process as reef is used to generate a bootable image.
Apollo Lake silicon requires a boot media region called IFWI which includes
assets such as CSE firmware, PMC microcode, CPU microcode, and boot
firmware.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1fb1184c5177437cc19824c14ec629440aaede80
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dcc0aa84fa
Original-Change-Id: Id92f0458548e3054d86f5faa8152d58d902f4418
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18039
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/431980
This commit adds the initial scaffolding for the Intel Leafhill CRB
with Apollo Lake silicon.
The google/reef directory is used as a template. This commit only
makes the minimum changes to Kconfig and Kconfig.name needed for
the build bot to not have issues.
BUG=none
BRANCH=none
TEST=none
Change-Id: I28d51ae70b98abafbbfd68b38a59b00074bc89ef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5f1f0538cf
Original-Change-Id: I088edee0e94ecfb4666fa31e08dbcfd24a81891b
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18038
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/431978
In order for PD charge events to properly notify the OS when a charger is
attached we need to enable the PD MCU device and event source from the EC.
Without this change the charging still happens, but the OS does not notice
and update the charge state icon in the Chrome OS UI.
BUG=chrome-os-partner:62206
BRANCH=none
TEST=plug in a charger to either port and see charge status updated to
indicate charging in the power_supply_info tool and the Chrome OS UI.
Change-Id: Ie4a2c145714636c43cf74168c119442cb0663635
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e949faec1
Original-Change-Id: Ia6f63ac719b739326d313f657a68005c32f45b8d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18209
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/431977
The devicetree settings were incorrect in a few places with
respect to the SOC and board design:
- IMVP8 VR workaround is for MP2939 and not MP2949 on Eve
- IccMax values are incorrect according to KBL-Y EDS
- USB2[6] is incorrectly labeled
- I2C touch devices do not need probed as they are not optional
- PCIe Root Port 5 should be enabled
- I2C5 device should not be enabled as it is unused
BUG=chrome-os-partner:58666
TEST=manually tested on Eve board
Change-Id: Ic863b0dce44a2f7f55b15a7a87513edc753d6a3c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: 949e34c3ee
Original-Change-Id: I74e092444ead4b40c6d8091b80a691d44e2c6c7d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18200
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431290
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to get quick boot speeds into recovery enable the
feature that allows for a separate recovery MRC cache.
This requires shuffling the FMAP around a bit in order to
provide another region for the recovery MRC cache. To make
that shuffling easier, group the RW components into another
sub-region so it can use relative addresses.
BUG=chrome-os-partner:58666
TEST=manual testing on eve: check that recovery uses the MRC
cache, and that normal mode does too. Check that if cache is
retrained in recovery mode it is also retrained in normal mode.
Also check that events show up in the log when retrain happens.
Change-Id: Id8e62117a9e679ef03e87a8563c377fc2a9a7c20
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: e00365217c
Original-Change-Id: I6a9507eb0b919b3af2752e2499904cc62509c06a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18199
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431209
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable the keyboard backlight as early in boot as possible to
provide a indication that the BIOS is executing.
Since this is bootblock it can't use the convenience function
for checking for S3 resume so just read the PM1 value from the
SOC and check it directly.
Use a value of 75% for the current system as that is visible
without being full brightness.
BUG=chrome-os-partner:61464
TEST=boot on eve and check that keyboard backlight is enabled
as soon as the SOC starts booting
Change-Id: I80274af9b3e032cc97403a180477b2d4742ad753
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: 367c9b328f
Original-Change-Id: I9ac78e9c3913a2776943088f35142afe3ffef056
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18197
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/431207
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The PP1800_S rail is turned off in S3. However, enabling internal
pullups on the pins which are connected to PP1800_S results in
leakage into the P1800_S rail. Fix this by disabling the internal
pullups on PP1800_S rail pins.
BUG=chrome-os-partner:61968
BRANCH=reef
TEST=measured leakage on PP1800_S rail. Gone with this patch.
Change-Id: I5c9a25ca617078a6ad48fe637abf0f397fda1ff5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aa6482e88e
Original-Change-Id: I5ae92b31c1a633f59d425f4105b8db1c9c18c808
Original-Signed-off-by: Aaron Duribn <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18189
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/430614
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
ELAN touchscreen device expects firmware to export GPIOs and ACPI
regulators for managing power to the device. Thus, provide the
required ACPI elements for OS driver to properly manage this device.
BUG=None
BRANCH=None
TEST=Verified that touchscreen works properly on boot-up and after
suspend/resume.
Change-Id: I0b3ec47e93b064f2195ec59bd9b5b8bc1927b3bb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bf68f2286c
Original-Change-Id: I78e0c35f60289afe338d140d90784a433ca534ae
Original-Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18163
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/430612
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Audio DMIC PLL needs to be ON in S0ix to support
Wake on Voice. This requires GPIO_79 and GPIO_80
to be configured as IGNORE IOSSTATE. So DMIC CLKs
will be ON in S0ix.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id6ddb380477762b37fe0b8fdcac762033048438b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c0eae6112f
Original-Change-Id: If91045a8664ce853366b670b9db38d620818fbab
Original-Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18155
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430713
This was already done in upstream when the patch was taken over.
Eliminate the difference.
BUG=none
BRANCH=none
TEST=none
Change-Id: I14545c81d0311130e6756c128b2653a5f92efe16
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427821
SPI controller need to access flash descriptors/SFDP during s0ix exit,
so all fast SPI IO can't be put into IOSTANDBY state. For reef, that
will be FST_SPI_CLK_FB, GPIO_97, GPIO_99, GPIO_100, GPIO_103 and
GPIO_106.
BUG=chrome-os-partner:61370
BRANCH=reef
TEST=Enter s0ix state in OS, after resume run flashrom to read SPI
content.
Change-Id: Ibeb71637b19c646a3390e98d083ae579144cb31c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8b89252f8a
Original-Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51
Original-Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18137
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430178
Tested-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Combine existing boards google/enguarde and google/ninja using
their common reference board google/rambi as a baseboard.
Variants contain board specific data:
- DPTF ACPI components
- I2C ACPI devices
- RAM config / SPD data
- devicetree config
- GPIOs
- board-specific HW components (e.g., LAN)
Additionally, some minor cleanup/changes were made:
- remove unused ACPI trackpad/touchscreen devices
- correct I2C addresses in SMBIOS entries
- clean up comment formatting
- remove ACPI device for unused light sensor
- switch I2C ACPI devices from edge to level triggered interrupts,
for better compatibility/functionality (and to be consistent
with other recently-upstreamed ChromeOS devices)
The existing enguarde and ninja boards are removed.
Variant setup modeled after google/auron
BUG=none
BRANCH=none
TEST=none
Change-Id: I9129c3d3eda15c1e91ff5bfd0aa5f9f891a2636c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce0a564198
Original-Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18129
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430177
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
1. Disable WP
2. Pass SD card detect info in ACPI
BUG=chrome-os-partner:60713
BRANCH=None
TEST=Verified that OS is able to detect SD card and read/write to it.
Change-Id: Id16f21dd70798b2e1c6e7af1d163e7089b66b46c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d093e4a387
Original-Change-Id: Ide84d4b86c0fac50a07520dfd76d6d3a921f2ecc
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18138
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430172
poppy schematics have undergone change after review, update
DQS and DQ Byte mappings based on the new schematics.
BUG=chrome-os-partner:61856
BRANCH=None
TEST= Build and boot all the poppy proto SKUs to OS.
Change-Id: I80eab8bc6fb486bab959ab308c93d1d3031247bc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b4a159706e
Original-Change-Id: Ie4532035f37c25540abb26122234f6e3346ede69
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18133
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/430171
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Baytrail SoC has a bug where in some cases the DisplayPort can hang
leading to a non-working display (it just stays black). To avoid this
hang, a patch was introduced in 02/2016
(1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort)
but per default not switched on so that each
mainboard can decide if it wants to use this patch or not.
Recently a new case of this bug was reported by Benoit Sansoni
(benoit.sansoni@kontron.com) and he requested to enable this fix per
default as it costs him a lot of time to find the cause and even the
already available fix in coreboot. To avoid this effort for someone
else in the future we can enable this fix per default as no negative
side effects are known and it is now tested at Siemens and at
Kontron on different mainboards with success.
As the goal is to enable this code permanently the config switch is not
longer needed and is removed.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8865b57dafe5df73e82255367562698b1a0a56b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: deed5fbebd
Original-Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/18109
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428264
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Current fw does not create ACPI device for
OS to recognize ELAN touchscreen.
List the touch screen in the devicetree so that
the correct ACPI device are created.
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5aadea9d76
Original-BUG=chrome-os-partner:61803
Original-BRANCH=reef
Original-TEST=emerge-pyro coreboot
Original-Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5
Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18086
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I63d4092acbb26602df9c501b8d87bfb3169ee79d
Reviewed-on: https://chromium-review.googlesource.com/428259
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Die if cbmem_add can't allocate memory for the hob pointer. This
shouldn't ever happen, but it's a reasonable check.
- fsp_broadwell_de already had a check, but it returned to someplace
inside the FSP. Just die instead.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic4a743faf8fdcc7b26c9fe2ed43ce10a539f79e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fb64d0b88
Original-Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623
Original-Found-by: Coverity Scan #1291162
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18092
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/428252
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The Lenovo T400 has a CPU socket that can fit quad cores.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4a6d7ef1e07175b9f776c63e7323347a00ac2485
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ccc042b821
Original-Change-Id: I585775ac9510cc7d2c2d731531f536c1a56b81e8
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18059
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/427475
Because Kconfig default values *ONLY* get set when they are first
configured, if you switch mainboards with an existing .config,
the values will not be set as expected for the new board.
This seems to confuse most users, so put a warning in a visible
location to let them know.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib4e35cf71c5777adbd15132ad8c7414aadfe4d27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f3e26796c4
Original-Change-Id: Ie6a9c2d139ecd841d654943f14c119ebafd632f2
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17939
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/427462
The commit 0ba3b2593b0c ("gru: Tuning USB 2.0 PHY to increase
compatibility") bypass ODT to set the max driver strength for
the Type-C otg-port, it works well on otg-port when connected
with USB2.0 devices.
Unfortunately, because the Type-C otg-port and host-port are
consisted in one USB2 PHY, so bypass ODT will have an effect
on both host-port and otg-port. I have tested the host-port
eye-diagram, the result shows that if we bypass ODT, the host-
port eye-diagram height will become to high, more than 500mv,
this may cause USB 2.0 high-speed enumeration failure.
This patch bypass ODT for host-port separately, and then we
can reduce the host-port driver strength without affecting
the otg-port driver strength.
BRANCH=gru
BUG=chrome-os-partner:60727
TEST=Boot system, run 'lsusb' command and check if the usb camera
and usb bluetooth are on usb 2.0 hub or usb 1.1 hub. If they are
on usb 1.1 hub, the issue happens. If not, try to run camera app
and then close camera app, repeat until find that the usb camera
is on the usb 1.1 hub.
Change-Id: Ia1f12182929673c5726df9f77f0903469b5c957a
Signed-off-by: William wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/425739
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Inno Park <ih.yoo.park@samsung.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Should have been included in 62902ca45d "sb/ich7: Use common/gpio.h to
set up GPIOs", which was not rebased on addition of this board.
Change-Id: If4547ee43ce6a7a6e4af67e9364613e48f989401
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18047
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425987
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is more consistent with newer Intel targets.
This a static struct so it is initialized to 0 by default.
To make it more readable:
* only setting to GPIO mode is made explicit;
* only pins in GPIO mode are either set to input or output since this
is ignored in native mode;
* only output pins are set high or low, since this is read-only on
input;
* blink is only operational on output pins, non-blink is not set
explicitly;
* invert is only operational on input pins, non-invert is not set
explicitly.
Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17639
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425981
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The bare ACPI MMIO address 0xFED80000 was used in multiple
AMD mainboard files as well as the SB800 native code. Reduce
duplication by using a centrally defined value for all AMD
ACPI MMIO access.
Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18032
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425978
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The console output is garbled until it is fixed in ramstage
by devicetree which sets the uart clock predivider correctly.
Change-Id: I6d6ec0febfec98a8d4a71e1476036c804cf5f08d
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17969
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425495
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Combine existing boards google/auron_paine and google/samus with new
ChromeOS devices auron_yuna, gandof and lulu, using their common
reference board (auron) as a base.
Chromium sources used:
firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...]
firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...]
firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table]
Additionally, some minor cleanup/changes were made:
- I2C devices set to use level (vs edge) interrupt triggering
- HDA verb entries use simplified macro entry format
- correct FADT table header version
- remove unused ACPI device entries / .asl file(s)
- clean up ACPI code (e.g., trackpad on Lulu)
- adjust _CID for trackpad on Lulu in order to not load non-functional
Windows driver (does not affect Linux)
- remove unused header includes (multiple/various)
- correct I2C addresses used for SMBIOS device entries
- correct misc typos etc
The existing auron_paine samus boards are removed.
Variant setup modeled after google/slippy
CQ-DEPEND=CL:425436
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8
Reviewed-on: https://chromium-review.googlesource.com/424869
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
