The commit 0ba3b2593b0c ("gru: Tuning USB 2.0 PHY to increase
compatibility") bypass ODT to set the max driver strength for
the Type-C otg-port, it works well on otg-port when connected
with USB2.0 devices.
Unfortunately, because the Type-C otg-port and host-port are
consisted in one USB2 PHY, so bypass ODT will have an effect
on both host-port and otg-port. I have tested the host-port
eye-diagram, the result shows that if we bypass ODT, the host-
port eye-diagram height will become to high, more than 500mv,
this may cause USB 2.0 high-speed enumeration failure.
This patch bypass ODT for host-port separately, and then we
can reduce the host-port driver strength without affecting
the otg-port driver strength.
BRANCH=gru
BUG=chrome-os-partner:60727
TEST=Boot system, run 'lsusb' command and check if the usb camera
and usb bluetooth are on usb 2.0 hub or usb 1.1 hub. If they are
on usb 1.1 hub, the issue happens. If not, try to run camera app
and then close camera app, repeat until find that the usb camera
is on the usb 1.1 hub.
Change-Id: Ia1f12182929673c5726df9f77f0903469b5c957a
Signed-off-by: William wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/425739
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Inno Park <ih.yoo.park@samsung.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Should have been included in 62902ca45d "sb/ich7: Use common/gpio.h to
set up GPIOs", which was not rebased on addition of this board.
Change-Id: If4547ee43ce6a7a6e4af67e9364613e48f989401
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18047
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425987
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Nothing from that header is used or even declared since
CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not selected on Intel
hardware.
Change-Id: I9101eb6ffa6664a2ab45bc0b247279c916266537
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18044
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425982
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is more consistent with newer Intel targets.
This a static struct so it is initialized to 0 by default.
To make it more readable:
* only setting to GPIO mode is made explicit;
* only pins in GPIO mode are either set to input or output since this
is ignored in native mode;
* only output pins are set high or low, since this is read-only on
input;
* blink is only operational on output pins, non-blink is not set
explicitly;
* invert is only operational on input pins, non-invert is not set
explicitly.
Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17639
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425981
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
cmos_post_init() is called in src/arch/x86/bootblock_simple.c, and
that function is reponsible for bootstrapping the cmos post register
contents. Without this function being called none of the cmos post
functionality works correctly. Therefore, add a call to lib/bootblock.c
which the C_ENVIRONMENT_BOOTBLOCK SoCs use.
BUG=chrome-os-partner:61546
Change-Id: I2e3519f2f3f2c28e5cba26b5811f1eb0c2a90572
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18043
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425979
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The bare ACPI MMIO address 0xFED80000 was used in multiple
AMD mainboard files as well as the SB800 native code. Reduce
duplication by using a centrally defined value for all AMD
ACPI MMIO access.
Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18032
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425978
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The console output is garbled until it is fixed in ramstage
by devicetree which sets the uart clock predivider correctly.
Change-Id: I6d6ec0febfec98a8d4a71e1476036c804cf5f08d
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17969
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425495
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Combine existing boards google/auron_paine and google/samus with new
ChromeOS devices auron_yuna, gandof and lulu, using their common
reference board (auron) as a base.
Chromium sources used:
firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...]
firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...]
firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table]
Additionally, some minor cleanup/changes were made:
- I2C devices set to use level (vs edge) interrupt triggering
- HDA verb entries use simplified macro entry format
- correct FADT table header version
- remove unused ACPI device entries / .asl file(s)
- clean up ACPI code (e.g., trackpad on Lulu)
- adjust _CID for trackpad on Lulu in order to not load non-functional
Windows driver (does not affect Linux)
- remove unused header includes (multiple/various)
- correct I2C addresses used for SMBIOS device entries
- correct misc typos etc
The existing auron_paine samus boards are removed.
Variant setup modeled after google/slippy
CQ-DEPEND=CL:425436
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8
Reviewed-on: https://chromium-review.googlesource.com/424869
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add rmu.bin to the list of files that exist only in the read-only
section (COREBOOT) of the SPI flash.
TEST=Build and run on Galileo Gen2.
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18031
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I30cbd3fb2ef1848807e4de4c479dc7a561c1faba
Reviewed-on: https://chromium-review.googlesource.com/425292
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Reviewed-on: https://chromium-review.googlesource.com/425291
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, some Intel 945 boards miss some or all of the time stamps
*1:start of rom stage*, *2:before ram initialization*, and *3:after ram
initialization*, so add them.
Use the same formatting as used for the board Lenovo X60, which already
has code for all the time stamps.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17993
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42
Reviewed-on: https://chromium-review.googlesource.com/425290
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the Kconfig value HAVE_MONOTONIC_TIMER and the routine to read the
TSC for the monotonic timer. Simplify the routine to get the TSC
frequency.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18002
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I806fb864b01e39277bf2d6276254b0543930c2f6
Reviewed-on: https://chromium-review.googlesource.com/425289
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add Kconfig values and early debugging code to better segment and debug
the early code in bootblock by using the SD LED as an indicator. Update
the help text for the debug Kconfig values to point to the various
failure locations.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/17985
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I1cd62eba3e9547cb1dd7f547aaec5d4827e14633
Reviewed-on: https://chromium-review.googlesource.com/425282
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix serial port configuration broken by how PCI configuration space was
referenced introduced by change 3d15e10a (MMCONF_SUPPORT: Flip default
to enabled).
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/17984
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I2ab52cf598795e94f1f16977f8d12b7fdd95e146
Reviewed-on: https://chromium-review.googlesource.com/425281
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This extra check is based on comparing CPU BSEL pins and reports in
MCH configuration. This gives false positives in the case of 1333MHz
CPUs which automatically get downgraded to 1067MHz by the northbridge
(max supported frequency by 945gc).
TESTED with Intel Xeon 5460 (does not boot but completes raminit)
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17997
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I34cb37912906c803abdad0adbd9c589ca86a67c7
Reviewed-on: https://chromium-review.googlesource.com/425279
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
amd_generate_powernow is never called by in lpc_slave_ops.
Move it to lpc_ops like on all other AMD southbridges.
TESTED on Gigabyte ga-m57sli-s4
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17977
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I7db036e681d591a19e15dd3eaafb88b72a41bea1
Reviewed-on: https://chromium-review.googlesource.com/425275
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If the cmos checksum is incorrect it should fall back to sane defaults.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17968
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: If16cfc73effd4a825d0cefcd30bfd0e48b2d9132
Reviewed-on: https://chromium-review.googlesource.com/425274
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Write gpio level twice to make sure the level is set
after pins have been configred as GPIO and to minimize
glitches on newer hardware.
Required to set correct GPIO layout on T500.
Tested on T500.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18012
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
Change-Id: I691e672c7cb52ca51a80fd29657ada7488db0d41
Reviewed-on: https://chromium-review.googlesource.com/425269
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
uart_fill_lb() was added to drivers/uart/uart8250mem.c, so when the
Oxford OXPCIe952 Kconfig option is enabled, we were getting an error.
"multiple definition of `uart_fill_lb'"
The new version of uart_fill_lb sets the regwidth depending on the
Kconfig symbol DRIVERS_UART_8250MEM_32, so if that's selected, don't
give DRIVERS_UART_OXPCIE as a choice.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17966
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ife24ab390553b10b2266809595c2e06463de708c
Reviewed-on: https://chromium-review.googlesource.com/425267
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The devicetree lacks the 'chip' option for the Super I/O,
which causes the Super I/O related entries to be ignored.
This also adds other LDN that are present on this Super I/O.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17965
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ida1b3c6575aa53bc7060070835c811665bdc1db1
Reviewed-on: https://chromium-review.googlesource.com/425263
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Because the binary repo is disabled by default, we get frequent
questions about why the build failed, relating to microcode in the
binary repository.
- Show an error saying that the file is missing instead of the typical
make error of no rule to build the file.
- Show a note encouraging users to try enabling the binary repo if it's
not enabled.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17940
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: If4148c18cfb781ed2932bd2ae4a289b621afdebf
Reviewed-on: https://chromium-review.googlesource.com/425259
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SPD revision 1.1 introduced FTB timings, an extra set of SPD values that
specify a more precise tCKmin, tAAmin, tRCDmin, tRPmin and tRCmin.
For backwards compatibility, the MTB is usually rounded up and the FTB
part is negative. For this reason some memories were not set up optimally,
as the FTB part was ignored and the resulting timing wasn't set to the
minimum value.
The tests were performed on a Lenovo X220 with two Micron 8KTF51264HZ-1G9E
(1866 MHz): reading only the MTB part, coreboot reports a tCKmin of
1.125 ns, corresponding to a working frequency of 800 MHz; with the
additional tCKmin FTB part (-0.054 ns) the new (rounded) value is
1.070 ns, valid for a 933 MHz operation.
Tested also with Ballistix DDR3-1866 SODIMM on Lenovo T420: the memory is
now detected as DDR3-1866 instead of DDR3-1600.
Some manufacturers (like Micron) seems to expect a small rounding on the
timings, so a nearest-value rounding is performed. If this assumption
isn't correct, an error up to ~2 ps can be committed, which is low enough
to be safely ignored.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/17476
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ib98f2e70820f207429d04ca6421680109a81f457
Reviewed-on: https://chromium-review.googlesource.com/425257
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use CONFIG_VBOOT to enable do_printk_va_list to match the conditionals
in include/console/console.h and the only caller is vboot/vboot_logic.c.
CONFIG_VBOOT is also selected for CONFIG_CHROMEOS.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/17967
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia115c74afa498a14d5edd6f7940ec2edc124516f
Reviewed-on: https://chromium-review.googlesource.com/425256
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Migrate duplicated enable_vmx() method from multiple CPUs to common
folder. Add common virtualization option for CPUs which support it.
Note that this changes the default to enable virtualization on CPUs
that support it.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17874
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Change-Id: Ib110bed6c9f5508e3f867dcdc6f341fc50e501d1
Reviewed-on: https://chromium-review.googlesource.com/425255
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With the default TCC activation offset value as 0 and Tjmax
temperature value as 100 degree C, Pcode firmware starts taking
prochot action at 100 degree C [Tjmax-Offset].
But before Pcode firmware starts prochot action at 100 degree C,
device is getting shutdown at 99 degree C due to DPTF critical
CPU temperature.
This patch sets TCC activation offset value to 10 degree C for
thermal throttle action to prevent this kind of shutdown.
BUG=chrome-os-partner:59397
BRANCH=None.
TEST=Built, booted on skylake and verified target offset value.
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17921
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I0811ef481a4b3ce4bd6ef24f2aa8160f44f9c990
Reviewed-on: https://chromium-review.googlesource.com/425253
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
TCC activation functionality has package scope. It was set
for all CPU in the system which is unnecessary.
In this patch TCC activation is being set by the BSP only.
BUG=chrome-os-partner:59397
BRANCH=None.
TEST=Built for skylake platform and verified the TCC activation
value before and after S3.
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17889
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Iacf64cbc40871bbec3bede65f196bf292e0149a6
Reviewed-on: https://chromium-review.googlesource.com/425252
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with
the ability to perform tx and rx of flash command and response at the
same time. Instead of introducing this notion at SPI flash driver layer,
clean up the interface to SPI used by flash.
Flash uses a command-response kind of communication. Thus, even though
SPI is duplex, flash command needs to be sent out on SPI bus and then
flash response should be received on the bus. Some specialized x86
flash controllers are capable of handling command and response in a
single transaction.
In order to support all the varied cases:
1. Add spi_xfer_vector that takes as input a vector of SPI operations
and calls back into SPI controller driver to process these operations.
2. In order to accomodate flash command-response model, use two vectors
while calling into spi_xfer_vector -- one with dout set to
non-NULL(command) and other with din set to non-NULL(response).
3. For specialized SPI flash controllers combine two successive vectors
if the transactions look like a command-response pair.
4. Provide helper functions for common cases like supporting only 2
vectors at a time, supporting n vectors at a time, default vector
operation to cycle through all SPI op vectors one by one.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17681
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236
Reviewed-on: https://chromium-review.googlesource.com/424871
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Define controller for fast SPI.
2. Separate out functions that are specific to SPI and flash
controller in different files.
BUG=chrome-os-partner:59832
BRANCH=None
BRANCh=None
TEST=Compiles successfully for chell and eve.
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17933
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I2fe0ef937297297339d4ea19dc37d3061caaa80c
Reviewed-on: https://chromium-review.googlesource.com/424870
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH is set, vbnv_cmos will try
to load VBNV from flash if the VBNV in CMOS is invalid. This is usually
correct, except the case of battery cut-off.
CMOS will always be invalid after battery cut-off if there is no RTC
battery (or if that is dead). However, in current implementation the
backup in flash is only updated in Coreboot, while the real battery
cutoff (and the clearing of cutoff flags in VBNV) is done in payload
(Depthcharge) stage. This will create an endless reboot loop that:
1. crossystem sets battery cutoff flag in VBNV_CMOS then reboot.
2. Coreboot backups VBNV_CMOS to VBNV_flash.
3. Depthcharge sees cutoff flag in VBNV_CMOS.
4. Depthcharge clears cutoff flag in VBNV_CMOS.
5. Depthcharge performs battery cutoff (CMOS data is lost).
6. (Plug AC adapter) Reboot.
7. Coreboot sees invalid VBNV_CMOS, load backup from VBNV_flash.
8. Jump to 3.
As a result, we should always clear battery cutoff flags when loading
backups from VBNV_flash.
BRANCH=glados,reef
BUG=chrome-os-partner:61365,chrome-os-partner:59615
TEST=emerge-reef coreboot bootimage;
Change-Id: I3250a3a179a7b0de9c6e401e4a94dcd23920e473
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/423460
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Enable an internal pull-up on the power button input as a quick
press is resulting in power button override being asserted.
BUG=chrome-os-partner:61312
BRANCH=none
TEST=tested on eve P0b to ensure quick power button press does
not result in a shutdown due to power button override.
Change-Id: I0eda182b62890edfcfdeec5b24b2d418be1897de
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424139
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize
& tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to
ApolloLake SoC when CONFIG_FSP_CAR is enabled.
Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17063
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25
Reviewed-on: https://chromium-review.googlesource.com/422956
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for
Cache-As-Ram initialization and teardown. Add fsp2_0 driver
support for TempRamInit & TempRamExit APIs.
Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17062
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2
Reviewed-on: https://chromium-review.googlesource.com/422955
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Values based on vendor bios and suggested by Arthur Heymans for FSB1067.
FSB1067:
The ratio 1067/800 is proportional to the ratio of EPBAR32(0x2c) bits:
0x1a / 0x14 ~ 1067/800
EPVC1IST:
The ratio is also proportional to FSB ratios: 0x9c / 0xf0 ~ 533/800.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17198
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib90e8ea1b82f2fcc3b5c199cace32a7f0aff4b5c
Reviewed-on: https://chromium-review.googlesource.com/422954
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit bf264e94 (i945:) adds a PCI reset to the romstage, and commit
bc8613ec (Fix i945 based boards) fixes that to use the correct
delay of 200 ms. This code was then copied over, when adding support for
the Lenovo X60.
The reset was related to the shipped crypto card on the Roda RK886EX and
Kontron 986LCD-M, so is not needed on the Lenovo X60. So remove it.
TEST=Build and boot on Lenovo X60t.
BUG=None
BRANCH=None
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17703
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ia37d9f0ecf5655531616edb20b53757d5d47b42f
Reviewed-on: https://chromium-review.googlesource.com/422951
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The user and supervisor counters could not be safely enabled
before as the register numbers were not finalized. Now that
everyone agrees, we can enable them. Until we are sure the
toolchains are caught up, we use the hardcode name with
the register names in comments. As soon as toolchains
settle down we'll do one more pass and convert to
the symbolic names.
Tested on lowrisc bitstream and SPIKE simulator.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17920
Tested-by: build bot (Jenkins)
Reviewed-by: Alex Bradbury <asb@lowrisc.org>
Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-by: Andrew Waterman <aswaterman@gmail.com>
Change-Id: I21fe5cac44fafe4b7806e004c179aa27541be4b6
Reviewed-on: https://chromium-review.googlesource.com/422950
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There was an assumption that all SPI controllers could
consume a full page of data to write. However, that
assumption doesn't hold when spi_crop_chunk() indicates
sizes smaller than page size. If the requested offset isn't
page aligned from the start then writes will fail corrupting
data since a page boundary isn't honored.
The spansion driver needed quite a bit more work to honor
the spi_crop_chunk() result. It now mimics the other
driver's code. Also, needed to add spi_crop_chunk() to
marvell/bg4cd SoC to make google/cosmos build. SPI obviously
doesn't work on that platform, but it fixes the build error.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17910
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Change-Id: I93e24a5a717adcee45a017c164bd960f4592ad50
Reviewed-on: https://chromium-review.googlesource.com/422949
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
An incorrect board name was propagated over various generations of mainboards.
Correct the comments for these. Addressing the todo items will come in a
later patch.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17903
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Change-Id: I4abd028fee5087955a7b6ba8d38f99c8207d24b4
Reviewed-on: https://chromium-review.googlesource.com/422947
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
