Modify the config file, consumed by amdfwtool, to use "sabrina" and
"SBR" named files.
TEST=build chausie using updated amd_blobs
BUG=b:220848549
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ia993644e67d14792d753cc74a957529d15be18f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The Sabrina APU has a maximum configuration of 4 physical cores with 2
threads each, so a total of 8 CPU cores.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I627ed78ffba6098726c9c8ec55b60665503240ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65068
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MCA bank names were checked against PPR #57243 Rev 1.53.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1b947e686a0306d4468203103f91107c15ececc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Sabrina slightly changed the names of microcode patches. Adding a
wildcard to support the new name without breaking current builds that
are using the placeholder CZN binaries.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I86caf0ba5c15f64a9a1f0e76a3186919e5e761a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65069
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sabrina uses the SVI3 spec for VID tables which is incompatible with the
SVI2 spec used on PCO/CZN. Move the defines from common to soc and
update the decoding for sabrina.
See NDA docs #56413 for SVI3 and #48022 for SVI2 VID tables
TEST=timeless builds on mandolin/majolica for PCO/CZN
build chausie and verify pstate power is correct in ACPI tables
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I915e962f11615246690c6be1bee3533336a808f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65001
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
It might be possible to have this used for more than x86, but that
will be for a later commit.
Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Use the equivalent cpuid in the microcode header to name the update file
in cbfs. This allows the SOC to directly locate its microcode file when
there are multiple processor revisions.
TEST: Loaded a chausie with sabrina, cezanne, and picasso microcode
files and booted. Verified that only the sabrina microcode file was
successfully loaded
Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Now that the FSP provides the ALIB ACPI table via a HOB, the PNOT power
notify method can call WAL1 which will then call ALIB to communicate the
current AC/DC state to the SMU.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic966b73aa28f329207f8d840ca5fb5f2bf6ec9b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64667
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All targets now use cbmem for the BERT region, so the implementation can
be common.
This also drops the obsolete comment about the need to have bert in a
reserved region (cbmem gets fixed to be in a reserved region).
Change-Id: I6f33d9e05a02492a1c91fb7af94aadaa9acd2931
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This removes the need to align BERT so that TSEG remains aligned.
Change-Id: I21b55a87838dcb4bd4099f051ba0a011a4d41eea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
On platforms where the bootblock is not included in CBFS anymore
(because it is part of another firmware section (IFWI or a different
CBFS), the CRTM measurement fails.
This patch adds a new function to provide a way at SoC level to measure
the bootblock. Following patches will add functionality to retrieve the
bootblock from the SoC related location and measure it from there.
In this way the really executed code will be measured.
Change-Id: I6d0da1e95a9588eb5228f63151bb04bfccfcf04b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There are efforts to have bootflows that do not follow a traditional
bootblock-romstage-postcar-ramstage model. As part of that CBMEM
initialisation hooks will need to move from romstage to bootblock.
The interface towards platforms and drivers will change to use one of
CBMEM_CREATION_HOOK() or CBMEM_READY_HOOK(). Former will only be called
in the first stage with CBMEM available.
Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The psp_notify_boot_done call is done at the entry of BS_PAYLOAD_BOOT,
so it's not guaranteed that the psp_set_spl_fuse call is done before the
psp_notify_boot_done call. Moving the psp_set_spl_fuse call makes sure
that it's done before the psp_notify_boot_done call. This also brings
the psp_set_spl_fuse call in line with the enable_secure_boot call that
sends the PSB fusing command to the PSP.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id76b462608c3d788cd90e73a64d18c8e8b89dbfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
mcfg->usb_phy is a pointer to a struct usb_phy_config. The config is
constant. Changing a constant is undefined behavior, so create a local
static instance of usb_phy_config that can be modified safely.
Change-Id: If9b76b869a5b0581f979432ce57cc40f1c253880
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add and use defines instead of magic values in fsp_m_params.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie0e33eb0af5310ab4610ea8951688464c4960260
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64126
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use sizeof instead of having a hard-coded struct length.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85dc2fce11d9a670b2037d8a6a694177cfaa2177
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The MP_IRQ flags can be used in the MP table and the ACPI MADT table.
Move them into acpi.h to avoid pulling in the full mpspec.h which is
only available on x86.
BUG=b:218874489, b:160595155
TEST=Build
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f1091b7629a6446fa399720b0270556a926401a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63845
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Platform Secure Boot (PSB) enablement via the PSP if it is not
already enabled. Upon receiving psb command, PSP will program PSB fuses
as long as BIOS signing key token is valid.
Refer AMD PSB user guide doc# 56654, Revision# 1.00, this document is
only available with NDA customers.
Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The postcar frame can now be a local variable to that function.
Change-Id: I873298970fff76b9ee1cae7da156613eb557ffbc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Setting up postcar MTRRs is done when invd is already called so there
is no reason to do this in assembly anymore.
This also drops the custom code for Quark to set up MTRRs.
TESTED on foxconn/g41m and hermes/prodrive that MTRR are properly set
in postcar & ramstage.
Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54299
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change matches what we already do for cezanne. It will allow the
GPIO controller to work correctly in windows.
BUG=b:175146875
TEST=Boot windows and verify GPIO controller binds correctly and touch
screen works. Also boot linux and verify touchpad still works.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I998e286de18d3e3f8b2fe610d17aef94a6cf5477
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
mcfg->usb_phy is a pointer to a struct usb_phy_config. The config is
constant. Changing a constant is undefined behavior, so create a local
static instance of usb_phy_config that can be modified safely.
Change-Id: Iedbc49109dcd1da9198fcb2a8f84e2b567cd8f86
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64130
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add and use defines instead of magic values in fsp_m_params.c. The
values will be updated to match the Sabrina FSP in a follow-up commit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I91da9e9d2b95e169dd73153766f24cf8afbfa4ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64128
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use sizeof instead of having a hard-coded struct length.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3c39d770a7719e30572e71b6a6c24fa2ad4a9426
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The bootblock.elf file gets embedded in the BIOSPSP part and loaded by
the PSP in dram. The top aligned bootblock in cbfs is unused.
Tested on Cezanne/Guybrush.
Change-Id: I72f0092e0e3628b388f6da6a417c2857a510b187
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The first target for the add_intermediate targets is always
$(obj)/coreboot.pre.
Change-Id: Iea2322ca1abd43900f3631b7965f07fed4235ca0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
This avoids compiler warnings on 64bit builds that complains about
casting pointer to non matching integer size.
Change-Id: I29fdb73ae1c0508796a21b650bf4fd1ac6688021
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Commit 198cc26e49 (soc/amd/common/block/
psp/psp_gen2: use SMN access to PSP) changed how the PSP registers are
accessed. Since the new method doesn't need to rely on a MMIO base
address to be configured, the read will always be successful and so
soc_read_c2p38 doesn't need to return an error status and can directly
return the value instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1abace04668947ba3223a107461a27dddc0a9d83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The eSPI decode range defines aren't and shouldn't be used directly from
outside of the common AMD eSPI code which provides functions to abstract
the register access, so move the defines from amdblocks/espi.h to
espi_def.h inside the common AMD LPC/eSPI support directory to limit the
visibility. The special I/O range decode bits need to stay in
amdblocks/espi.h since those are used in the devicetree. Also update the
indentation in espi_def.h so that the defines line up properly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic4ea30a1a6f10e94d88bf3b29f86dee2da6b39b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64053
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sabrina has more eSPI decode ranges than Picasso or Cezanne. Those
registers are however not in one block where it's easy to calculate the
addresses of a register from the index of the decode range. Within one
group of decode range registers it's still easy to calculate the
register address, so move the base address from within the macro to the
instantiation of the macro as a preparation for adding the support for
the additional ranges.
TEST=Timeless build results in identical binary for Mandolin
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id309d955fa3558d660db37a2075240f938361e83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Since we can't rely on the MMIO base address in the PSP_ADDR_MSR MSR to
access the PSP mailbox registers, switch to using the SMN mapping of the
PSP mailbox registers. The PSP SMN base address is taken from the amdgpu
driver in the Linux kernel.
BUG=b:229779018
TEST=Mandolin still boots successfully and there are no errors/warnings
about possibly PSP-related things.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9d17e523e9ae8d8e14ecedc37131a81f82351487
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64034
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CORE_2_PSP_MSG_38_OFFSET and CORE_2_PSP_MSG_38_FUSE_SPL are only used in
psp_gen2.c, so move them into this file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67cc2ff63d1c0322b514521975f3ce0f9b1cf5b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
I find it difficult to constantly decode the registers when reading
them. Let's print out something that's easier to parse.
BUG=b:228289365
TEST=boot guybrush and see status codes printed
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6c9d98cf43f340cf50e12c93b4c35187de9bb750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Silently failing makes it hard to debug when something goes wrong.
BUG=b:228289365
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7423a7011e7656414155386c014a9a0f2fad4abf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Drop struct pspv2_mbox and access the PSP mailbox via their offsets into
PSP MMIO region.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib665d7ae19deae07d6a69c11ba8cf44e45ea4e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63966
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't use unnamed redefinitions of the pspv2_mbox_command union when the
union definition can be used instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3757db45272f11bb47e5106ad9054c0a9ca0cd52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The pspv2_mbox struct contained an unnamed union that covered the 32
bits of the command register of the PSP v2 mailbox. Since the pspv2_mbox
struct is mainly used for hardware register accesses and the union part
is mostly used to access the different bits before/after writing/reading
the command register, split this functionality. For the register access
a command field is added to the pspv2_mbox struct instead of the unnamed
union and for accessing the separate bits of the command register a new
named union is added.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If3f00b6fd73c3f749154b77b940e6d5aa385ec49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The cmd_response field in the pspv2_mbox struct is the buffer used to
pass data to the PSP and back to the x86 side, so rename it to buffer.
This also aligns the code a bit more with the reference code. Also
rename the wr_mbox_cmd_resp function to wr_mbox_buffer_ptr.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22c8971b07b3dedcc2e6e50e93c98d69ec7379e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63962
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pspv[1,2]_mbox struct is only used in psp_gen[1,2].c, so move those
definitions from the common psp_def.h to the specific psp_gen[1,2].c
files. Also fix the struct name in the comment about pspv1_mbox.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0c95e9a6e292b90e0d147c57f59828a9b41e4b82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63960
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size. intel/apl is an exception since the
bootblock size is limited to 32K.
Change-Id: I5e02961183b5bcc37365458a3b10342e5bc2b525
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Sabrina added the ALERT_ENABLE bit. Set it to enable the eSPI_ALERT#
line.
BUG=b:227282870
TEST=Boot skyrim and verify keyboard works
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2a193ca454692bf13b707401079bd9edf026ef5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
This bit is new on sabrina. We need to enable it after initialization
has completed.
BUG=b:227282870
TEST=Boot skyrim to OS and verify keyboard works
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I795275993589e20c1d09674232ecff782c491335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
We don't currently have ALIB plumbed through. Disable the ALIB call to
remove ACPI errors during boot.
BUG=b:228496169
TEST=Boot skyrim and no longer see ALIB errors
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iad45bcda326597ebfc8b9c403de5b4a934b0bbc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63841
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
