Commit graph

10,617 commits

Author SHA1 Message Date
Marcello Sylvester Bauer
45a354fe78 mb/lenovo/*: Add vboot RO FMAPs on 12MiB devices
Tested on W530

Change-Id: I9be0c5e06fcb8287d32171cb72dabb5fcf047e7a
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39450
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 09:48:44 +00:00
Patrick Rudolph
c02bda0f06 acpi: Bump FADT to revision 6
Some of the revision 4 FADT fields were already updated to ACPI
spec revision 6, but not all of them. In addition the advertised
FADT revision was 3.

Implement all fields as defined in version 6 and bump the advertised
FADT revision to 6.

Also set all used access_size fields and x_gpe0_blk to sane values
as Windows 10 verifies those fields starting with FADT revision 5.

Fixes: https://ticket.coreboot.org/issues/109

Tested on Windows 10.

Change-Id: Ic649040025cd09ed3e490a521439ca4e681afbbf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-04-13 23:32:15 +00:00
Varun Joshi
2255ebaa23 mb/google/deltaur: Add support to enable GbE on variant
- Configure devicetree for enabling GbE on variant
  and remove from baseboard.
- Configure Kconfig to enable GbE region.
- Configure fmd to incorporate GbE.

BUG=b:151102809
Cq-Depend: chrome-internal:2843183
Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I1c36b132546049e3e775585c41164072f4ece73e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2020-04-13 20:28:18 +00:00
Anil Kumar
c6f5b05cf3 mb/google/deltaur: Return SKU ID info
For Deltaur and Deltan variants return proper SKU ID based on EC
firmware type and sensor detect GPIO value

BUG=b:152544516
TEST=make build successful for deltan

Change-Id: I20a497739e5062400b093648c3a634203dec6105
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-13 20:26:54 +00:00
Varun Joshi
06684979f9 mb/google/deltaur: Update onboard memory config
Update dq, dqs map based on deltan schematics.
Configure memory to read SPD.

BUG=b:151702387

Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-13 20:24:59 +00:00
Srinidhi N Kaushik
3907a64a48 mb/google/volteer: enable Early Command Training
Update memory configuration on Tiger Lake platform to enable Early
Command Training. This feature was not supported before FSP v2527.

BUG=b:150357377
BRANCH=None
TEST= Build and boot volteer

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I674c30f4dfc1af6c0c4a460d66684545a190caf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40023
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13 15:51:01 +00:00
Aaron Durbin
4ed96f2443 ec/google/chromeec: add smbios_mainboard_manufacturer()
When EC_GOOGLE_CHROMEEC_SKUID is selected provide an
implementation of smbios_mainboard_manufacturer() so the code
doesn't need to be duplicated in the mainboards.

BUG=b:153767369

Change-Id: Ib65fe373a79d606cffcba71882b0db61be5a18c3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-13 15:03:48 +00:00
Ronak Kanabar
da968d5f2e mb/intel/jasperlake_rvp: Enable S0ix for JSLRVP
Enable S0ix from devicetree for JSLRVP

TEST= Build, boot JSLRVP and Verified S0ix is
working by running "echo freeze > /sys/power/state"
from kernel console.

Change-Id: Iedbd7ce9db546f8dc6cb3343fa624abde0ef0d3f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-04-13 06:45:10 +00:00
Maulik V Vaghela
d7564dc1b9 mb/intel/jasperlake_rvp: Enable audio
Enable audio for Jasper Lake RVP board. It has 2 Audio codec chips
connected on I2C0: DA7219 and MAX98373

1. Enable Kconfig to enable I2C drivers for both chips.
2. Make necessary devicetree changes to enable FSP UPDs and ACPI entry
   for I2C0.
3. Enable audio related GPIO configurations.

BUG=None
BRANCH=None
TEST=Checked that dmic and speaker are functional on Jasper Lake RVP

Change-Id: Ibf76eb36c478bd33cbc0c86099236452b397fcc5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39695
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13 06:44:51 +00:00
Scott Chao
2a203c50ef mb/google/kukui: correct board name
Modify board name from "Kadadu" to "Kakadu"

BUG=b:153590144
TEST=CPU log show "Starting depthcharge on Kakadu..."
BRANCH=kukui

Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com>
Change-Id: Ibf387b0e0153315ff2ab5c19381db44a61c14e96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40283
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11 09:32:42 +00:00
Elyes HAOUAS
fd8de1860d src/mb: Remove unneeded spaces before/after tabs
Change-Id: I02979a0632a7b356985f96c3ba239daba178b4e3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39989
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10 22:30:06 +00:00
Jake Mannens
a0722870a8 mb/lenovo/t420s/devicetree.cb: Fix PCIe port definitions
The NEC uPD720200A USB 3.0 controller on the T420s is actually
connected to PCIe root port #5 on the PCH, not #7. Enable RP#5,
disable RP#7 and update comments accordingly.
Test=USB 3.0 controller shows in `lspci`

Change-Id: I21ac72fd5632e552bdcdbd573cf92b433ed545ff
Signed-off-by: Jake Mannens <jakem_5@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-10 22:28:00 +00:00
Karthikeyan Ramasubramanian
d38108f26f mb/google/dedede: Add Synaptics Touchpad configuration for waddledee
TEST=Build and boot the mainboard. Ensure that the touchpad is
operational.

Change-Id: I937462cd3992a884194bbd1759a0802a147e925a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-10 19:32:59 +00:00
Karthikeyan Ramasubramanian
e9eb4d5df9 mb/google/dedede: Add weak pull-up for EC_AP_PWR_BTN_ODL gpio
According to the EDS, EC_AP_PWR_BTN_ODL has a default internal pull-up
of 20K. Retain it during the GPIO pad configuration.

BUG=b:150985246
TEST=Boot the mainboard.

Change-Id: I042ba70f78fca1a5b9eda30029df97b3f8e65656
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39852
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10 19:31:18 +00:00
Nico Huber
2f8ba69b0e Replace DEVICE_NOOP with noop_(set|read)_resources
`.read_resources` and `.set_resources` are the only two device
operations that are considered mandatory. Other function pointers
can be left NULL. Having dedicated no-op implementations for the
two mandatory fields should stop the leaking of no-op pointers to
other fields.

Change-Id: I6469a7568dc24317c95e238749d878e798b0a362
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10 11:50:22 +00:00
Nico Huber
a461b694a6 Drop unnecessary DEVICE_NOOP entries
Providing an explicit no-op function pointer is only necessary for
`.read_resources` and `.set_resources`. All other device-operation
pointers are optional and can be NULL.

Change-Id: I3d139f7be86180558cabec04b8566873062e33be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10 11:25:04 +00:00
Elyes HAOUAS
c2e796290a mb/*/*/hda_verb.c: Improve code formatting
Change-Id: I294ea867678ad77e454873ecf4948bf2d12c9f80
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-10 00:13:12 +00:00
Elyes HAOUAS
17419ff948 mb/intel/icelake_rvp/variants/icl_u: Improve code formatting
Change-Id: I2a87e5c0f598d665f1c64ac8cfe235918326d1d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-09 23:49:47 +00:00
Elyes HAOUAS
3408a0ef0c mb/intel/d945gclf: Improve code formatting of devicetree
Change-Id: I3c8d430a10562edd4404d322e78f603cae191026
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-09 23:49:12 +00:00
Edward O'Callaghan
200f02a518 mb/google/hatch: Allow variants to not necessarily be laptops
In some cases Hatch variants are not laptop form-factors such
as Puff. Ensure that the base configuration does not assume
the form factor and allow variants to elect their intended
use-case.

Note that the issue is that early ec sync needs to be
disabled for EFS2 to function correctly, see commit 6daa8c3ba5
from the FIXME line. The relationship is that desktops do not
have a battery.

BUG=b:152951181
BRANCH=none
TEST=none

Change-Id: I15dc9efa51e9d61297868df287879dfb62909e33
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40252
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-09 13:43:33 +00:00
Arthur Heymans
dc98bed869 mb/intel/d510mo: Add vbt file
Add vbt file extracted from the vendor UEFI blob version 0524.

Change-Id: Idd39065e9cf5a420317d79695cf032713173eeab
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-04-09 08:51:51 +00:00
Seunghwan Kim
e0b41fd12e mb/google/nightfury: Update DPTF parameters
Apply initial DPTF parameters for nightfury from internal thermal team. Will update after further thermal/performance tuning.

BUG=b:149226871
BRANCH=firmware-hatch-12672.B
TEST=built and verified FAN worked by DPTF active policy

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I712bdd8edc999ef7ee33f4adf21893be12e86bec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-07 23:18:26 +00:00
Michał Żygowski
869ac71483 Revert "mb/pcengines/apu2: add reset logic for PCIe slots"
This reverts commit c04871a398.

Reason for revert: Many apu2 users reported issues with PCIe modules
detection in mPCIe2 slot (4x GFX PCIe). The regression was not caught
by 3mdeb validation stands and hardware configuration.

Change-Id: I609bf4b27c88a9adf676d576169f5ca26726ee86
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40147
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-07 12:07:15 +00:00
Tommie
1b7fc32a54 mb/google/octopus/variants/phaser: Disable xHCI compliance mode
Since the first LFPS timeout causes xHCI to enter compliance
mode, the SS hub cannot be enumerated. The resolution is to
disable xHCI compliance mode.

BRANCH=octopus
BUG=b:149723583
TEST=Verified USB operation successfully.

Signed-off-by: tong.lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: I3e6ab6ec0c4865cf2467da900f13d18468ff356f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marco Chen <marcochen@google.com>
2020-04-07 03:50:08 +00:00
Angel Pons
47f26dbe15 mb/google/rambi: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I0dea26da28a2879e34593907fef6f984317c347f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40191
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:56:02 +00:00
Angel Pons
2712398a69 mb/google/poppy: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Idfc7a5713e231c4756b5faca8984c6598fe1e65a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40190
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:55:51 +00:00
Angel Pons
d28443e5c6 mb/google/slippy: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I74fd273aff05e6635d4964f3614c2f1dd5562b4b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:55:32 +00:00
Angel Pons
08b5280c9f mb/google/octopus: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I8076155330100982de82d410b6579ac99ed89e7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40187
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:55:20 +00:00
Angel Pons
2e8a4b0498 mb/google/stout: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Ic3314eb6137a6fc9fa1f90685f37223ca1580cb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40197
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:55:08 +00:00
Angel Pons
d9d1d20c97 mb/google/sarien: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Ia64c49aed694eac1f98d176c646a60597c8ae66a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40193
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:54:54 +00:00
Angel Pons
11ba353806 mb/google/kukui: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I377ee2c9dfa3113f88237bd6ea79031a79f18ad5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40180
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:54:39 +00:00
Angel Pons
b5a2a52bee mb/google/kahlee: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I78f386eb47fc9b91992884e309dbbf33fb3d4e92
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40179
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:54:27 +00:00
Angel Pons
952f6b0a77 mb/google/reef: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I57e6790e49032902703ba84b68f285749aab2573
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-06 13:54:16 +00:00
Angel Pons
feedf23de0 mb/google/link: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Iddcf70e9a0976cfe2e5fb6d557bfcd22ab1f68cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40181
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:54:04 +00:00
Angel Pons
96d93d142e mb/google/parrot: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I0f41016ea678f63f386c1ae7006b7221a05f6fd9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-06 13:53:47 +00:00
Angel Pons
e816d807b9 mb/google/volteer: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I8e2aaf681ba3543cfcd400d21f8e94454e9b1c98
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40202
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:53:37 +00:00
Angel Pons
2e53038cf9 mb/google/veyron_rialto: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Ib28acdb91c5eb0c06413edfab62d6737932946f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40201
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:53:17 +00:00
Angel Pons
7caffce31f mb/google/storm: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I22232d098d34b9a642da157d07978b8d044926ff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-06 13:53:07 +00:00
Angel Pons
68dd0d53d6 mb/google/nyan_blaze: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Ie2f0dac5a0dee26b965616d410e343569588db7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-06 13:52:53 +00:00
Angel Pons
94d079ac5d mb/google/veyron_mickey: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Icabeae8d5c6c8be8dc284354e1523cec04c9fe30
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40200
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:52:39 +00:00
Angel Pons
cc98db367c mb/google/peach_pit: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Ie27b19e2a15855def11e366a86e43776ceb71083
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-06 13:52:29 +00:00
Angel Pons
141402dfc7 mb/google/oak: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I46f098f38576dee14b34789c24ad5513ed47fac1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-06 13:52:13 +00:00
Angel Pons
c31c09fe0e mb/google/veyron: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I267f0f989112907f45868c1bdfd3fa117851e586
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-06 13:51:07 +00:00
Angel Pons
57566307a8 mb/google/nyan_big: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Ie6fb3a47a6ac39a435605ef6aeb30f8001c0a166
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-06 13:50:56 +00:00
Angel Pons
8d0e929efd mb/google/smaug: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I5e297e7c68d5c2646d1a086ae1a5b64fef7ed730
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-06 13:50:43 +00:00
Angel Pons
163030bcd3 mb/google/nyan: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Iea5f9af845fda3ffff303aed402edea8b9eb219a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40183
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:50:29 +00:00
Angel Pons
ef975087cd mb/google/mistral: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I3be3f10d1f9399796f89071fb35c8e222ef93069
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-06 13:50:17 +00:00
Angel Pons
378a955d1b mb/google/trogdor: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I2ba6f07aa2568c6abf20d6c92ec26bc97f4acdbb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40198
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:50:06 +00:00
Angel Pons
af4ecc24d4 mb/google/jecht: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I90a3b2384797a15d5ac7f3cf9df808a5cfb1dc8c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40178
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06 13:49:50 +00:00
Angel Pons
b6636b0ea8 mb/google/hatch: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: If85e246550abe323d6a2a7c6301e8e91858cbe3a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-06 13:49:40 +00:00