Apollo Lake seems to start with PCIe root ports unusable/uninitialized
before FspMemoryInit() is called and FSP-M properly initializes these
root ports.
However, we need the root ports accessible before FspMemoryInit() in
certain cases, such as emitting POST codes through a PCIe device.
For the initialization to happen properly, certain register writes
specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter
3.3.1 have to be done.
BUG=none
TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check
that the POST codes are emitted before FspMemoryInit().
Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68223
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On nissa, the pre-x86 time is not part of the 1s firmware boot time
target. Including the pre-x86 timestamps causes confusion since the boot
time appears to be greater than 1s, so disable the Kconfig on nissa.
We're not doing any analysis or optimisation of the pre-x86 time on
nissa anyway, this work will start from MTL onwards. Also, the Kconfig
is already disabled on the brya firmware branch, so this will result in
the same behaviour as brya.
Before:
Total Time: 1,205,840
After:
Total Time: 995,300
BUG=b:239769532
TEST=Boot nivviks, check "1st timestamp" is the first timestamp.
Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68553
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not all kahlee variants use the RT5682 audio codec, so split the
baseboard audio ACPI into two parts and only include the asl for
the codec(s) actually needed for a given variant.
TEST=build/boot aleena, liara variants and verify no ACPI present
for RT5682 codec (which is not present on the boards).
Change-Id: Icb7df4f8e51495ad3cb40113cd00810fd27dcd00
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Built from a mixture of autoport output, other variants, schematics and
expert guesswork. I don't have this board, but the code has been tested
by someone else and boots successfully (first try) with TianoCore. It's
reasonable to assume most things work, as this board is very similar to
the already-supported variants.
Change-Id: I3d8df483e5573f77782b7d18b1410b391bfe387d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61541
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add two new types for MDN DDI descriptor
BUG=b:228284940
TEST=Normal boot and S0i3 cycles
Signed-off-by: Jason Nien <finaljason@gmail.com>
Change-Id: I02793f032f9855dac202a5aca8666c26426d6cb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66847
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Create the gladios variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:239513596
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_gladios
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I3dc99d97d8e30d9641f56616222dd68e3a0d548d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We use the name of the APCB file repeatedly, so put it into a variable
so that it's easier to update.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I8684db2f7b2d68f0354e37bd8cdfc4f9cab44b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change is to skip sending the MBP HOB since coreboot doesn't
use it and also helps to reduce the boot time by ~40 ms.
Boot time data
Before:
* 955:returning from FspSiliconInit 1,656,985 (274,416)
After:
* 955:returning from FspSiliconInit 1,593,036 (233,286)
BUG=b:252410202
TEST=Verified that boot time is reduced by ~40 msec.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I0d4f66940529b8d38d9658c769feba8b5c9b715e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68418
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
We need to boot eMMC for modem calibration, there is not need for BIOS
to initialize NVMe anymore as the kernel will do so. Removing the pci
device from the device tree as a first step.
BUG=b:185426670, b:254281839
BRANCH=None
TEST=Boot after removing from the herobrine device tree.
Change-Id: I802dd1361bc56a24ab3d65e6782bc611b7b75ee3
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNCP3MLYR-N6E 1 (0001)
MT62F2G32D8DR-031 WT:B 2 (0010)
H9JCNNNFA5MLYR-N6E 3 (0011)
BUG=b:250470704, b:247683159
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I34584092c938539c91d65501ebe34b00212b34d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Craask does not have a SAR proximity sensor.
BUG=b:253387689
TEST=Dump ACPI SSDT and verify SX9324 related entries are not present.
Change-Id: Ia0e3eb6dba82594ca27040d6ab0197da6095f510
Signed-off-by: Victor Ding <victording@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68564
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Librem Mini has a UART (accessible with soldering), which is very
useful for work on coreboot. It can be used for coreboot/SeaBIOS/Linux
boot logs, or as a general purpose UART.
Change-Id: I38ad5f19da6af5ed286ad3583f34b824a3660916
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68551
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the Intel iGPU as primary video adapter if enabled according
to EEPROM settings. The default is to use the ASPEED BMC as primary
video adapter, which only has a VGA output and the remote KVM output.
For now, use the FSP GOP driver to light up the iGPU. There are several
issues with libgfxinit on the Hermes, probably due to the unusual setup
of the iGPU's display outputs. They are routed to a mezzanine connector
for a piggy-back sub-board, of which there are two models. The Poseidon
piggy-back has two DisplayPort outputs and an HDMI output coming from a
MegaChips LSPCON. The Avalanche piggy-back routes all three DisplayPort
outputs from the iGPU into a FPGA, which acts as a DisplayPort sink.
Note that the FSP GOP only initializes at most 2 iGPU display outputs.
However, all three outputs function properly once OS (Windows, Linux)
graphics drivers take over.
Additionally, update the config file that Prodrive uses to build
coreboot images so that the iGPU can be used as primary.
TEST=Verify that the iGPU's outputs work properly in pre-OS, Windows and
Linux, on both the Poseidon and Avalanche piggy-backs.
Change-Id: I24d9ebc2055dc246e7f257aa2f3853b22c8af370
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62649
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ISH build target used for nissa is called adl_ish_lite: CL:3925007,
and by default the binary is installed as
/lib/firmware/intel/adl_ish_lite.bin
We could change the installed name, but it's nicer to keep it consistent
with the build target, so change the name in coreboot instead.
BUG=b:234776154
TEST=Build and boot nirwen, check firmware name is updated in SSDT
Change-Id: I983a38d08e758cf5a12a3f91a601c7e57d42c0cb
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
1. Set the PL1, PL2 and PL4.
2. Set PsysPL2 and PsysPmax.
BUG=b:253380352 b:253542746
TEST=Compare the measured power from adapter with the value of 'psys'
from the command 'dump_intel_rapl_consumption'.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I0a7ff64689b39e7754e0aed2f6869881a682fc93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68437
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Remove the ACPI ALS device from the EC configuration for newer devices,
because some do not have light sensors, and those who do have their ALS
presented through the new EC sensor interface already.
Inspired from commit ("f13e250152 ("UPSTREAM: mainboard/google/eve: Remove ACPI ALS device")
BUG=b:253967865
BRANCH=none
TEST=Boot a device and ensure that 'acpi-als' device is not present
in /sys/bus/iio/devices.
Change-Id: Ibcfa9e8c5a4679d557150998fd255789d3f8a272
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68493
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SAR-related Kconfigs are only used by ChromeOS, and should be guarded
properly as such (as most other boards do).
TEST=build glados w/o CONFIG_CHROMEOS, verify SAR-related Kconfigs not
selected.
Change-Id: Id8abf68ed2e9720b5580f7965208dbe36460af07
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68458
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SAR-related Kconfigs are only used by ChromeOS, and should be guarded
properly as such (as most other boards do).
TEST=build reef w/o CONFIG_CHROMEOS, verify SAR-related Kconfigs not
selected.
Change-Id: I4fe3092e620bcbc33b0411ea69e55154fc118aa4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68457
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SAR-related Kconfigs are only used by ChromeOS, and should be guarded
properly as such (as most other boards do).
TEST=build sarien w/o CONFIG_CHROMEOS, verify SAR-related Kconfigs not
selected.
Change-Id: I424033e087bc37c651a922273718fc229b720448
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68456
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the GSC is ready for the next transaction, it triggers a
GSC_AP_INT_ODL (active low) pulse with 100us duration to notify the AP.
Currently the TPM IRQ is configured as EDGE_RISING. Changing it to
EDGE_FALLING would speed up each register access by 100us. On Kingler,
this saves 20ms for the boot time (0.93s -> 0.91s).
BUG=b:235185547
TEST=emerge-corsola coreboot
TEST=Kingler booted without TPM errors
BRANCH=none
Change-Id: Id282e0f35694bd151781845cbd5aa4b389a30ddc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
X9SAE has a PS/2 controller for keyboard and mouse but its definition
in ACPI used to be missing, and X9SAE used to use a generic SuperIO
support initially generated by autoport, so the full NCT6776 support
is added here like x9scl.
Test result:
Log lines like
i8042: PNP: No PS/2 controller found.
i8042: Probing ports directly.
serio: i8042 KBD port at 0x60,0x64 irq 1
serio: i8042 AUX port at 0x60,0x64 irq 12
mousedev: PS/2 mouse device common for all mice
become
i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at
0x60,0x64 irq 1,12
serio: i8042 KBD port at 0x60,0x64 irq 1
serio: i8042 AUX port at 0x60,0x64 irq 12
mousedev: PS/2 mouse device common for all mice
and more sub-devices within SuperIO is handled by the PNP driver.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ie5e73e8c3fc4e57c6683d7a7ca70e96c64dd9366
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable PMC in devicetree so that resources are allocated properly
for it.
Tested on StarLite Mk III & IV, and both can power on correctly.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib4384b55751a9979e470dd04f6814d4ca170ff34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67409
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reset the XHCI controller prior to S5 to avoid XHCI preventing shutdown.
Linux needs to put the XHCI into D3 before shutting down but the
powerstate commands do not perform a reset.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3be70443eb85a7dff8055c9de0ca2fd89f4fc88d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67678
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This AMD reference board is called Pademelon and not Padmelon, so fix
the name in coreboot. Also update the corresponding documentation.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id1c7331f5f3c34dc7ec4bc5a1f5fe3d12d503474
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Add initial fw config as per config.star.
BUG=b:253199788, b:245158908, b:244113761, b:244012065
TEST=emerge-rex coreboot. Make sure that ACPI tables are equivalent
before and after this change with CBI.FW_CONFIG set to 0x1561.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I66f8b3e4ab414c03b8d63fdd31e0f3f424619340
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68220
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When fw_config is unprovisioned, devicetree will disable all probed
devices. However, boot-critical devices such as storage devices need to
be enabled.
As a temporary workaround while adding devicetree support for this,
remove the fw_config probe for storage devices so that all storage
devices are always enabled. On eMMC SKUs, UFS and ISH will be disabled
by the PCI scan anyway. On UFS SKUs, eMMC is not disabled by the PCI
scan, but keeping it enabled should have no functional impact, only a
possible power impact.
BUG=b:251055188
TEST=On yaviks eMMC and UFS SKUs, boot to OS and
`suspend_stress_test -c 10`
Change-Id: I6b3a20f3c14d5e9aa8d71f6ca436b5a682310797
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68365
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1.Change the TPM I2C freqeuncy to 1 MHz for xivu.
2.Config same settings as the baseboard for I2C buses 1-5.
BUG=b:249953477
TEST=On xivu, all timing requirements in the spec are met.
Frequencies:
1. I2C0 (TPM): 974.3 Khz
2. I2C1 (TouchScreen); 375.5 Khz
3. I2C3 （Audio): 389.0 Khz
4. I2C5 (Touchpad): 388.5 Khz
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I33f712c14978b95f3a4da82d6f1f5fbae1283b17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
The PCIe port descriptor list seems to be specific to Merlin Falcon and
Prairie Falcon has a different PCIe root port configuration. Since I
neither have the board nor the different APUs, I just add a comment
about this instead of trying to come up with a PCIe port descriptor list
that may or may not work properly on Prairie Falcon APUs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8e1eb67a8f684297bbefc6e2593250d7bd45593f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
