This removes the dev_index argument from the google_chromeec_reboot
API. It's always set to 0, so don't bother passing it.
BUG=b:258126464
BRANCH=none
TEST=none
Change-Id: Iadc3d7c6c1e048e4b1ab8f8cec3cb8eb8db38e6a
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69373
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We don't need to check the lower level error code to determine if an EC
call succeeded. Simply check the return value of the call.
BUG=b:258126464
BRANCH=none
TEST=none
Change-Id: Iaf0795b0c1a2df0d3f44e6098ad02b82e33c5710
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69372
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
google_chromeec_get_uptime_info() doesn't need to return an error code
from the lower level calls for the caller to interpret. It is more
appropriate to return a success/failure boolean.
BUG=b:258126464
BRANCH=none
TEST=none
Change-Id: I3e27b8b4eed9d23e6330eda863e43ca78bb174a3
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69371
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The EC_CMD_USB_PD_PORTS host command returns a
struct ec_response_usb_pd_ports, not a
struct ec_response_charge_port_count.
Luckily, both structs have the same memory layout, so this is simply a
name change.
BUG=b:258126464
BRANCH=none
TEST=none
Change-Id: I0d7710ca8a45f0ea3939f58bbba6bab31ff41919
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69370
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Simplify the implementation of setting the keyboard backlight PWM
value. Host command stubs typcially don't need to examine the host
command's return value as stored in cmd_code because that level of
detail is not very interesting. Higher value error codes are returned in
actual result structures.
This host command can return EC_RES_ERROR for out of range PWM values
which is already a generic error and unlikely to happen since we already
limit the range to 0..100 here. Finally, none of the callers in coreboot
check the return value.
BUG=b:258126464
BRANCH=none
TEST=none
Change-Id: If17bc4e31baba02ba2f7ae8e7a5cbec7f97688c5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69369
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an ACPI method to handle EC_HOST_EVENT_PANIC (bit 24) events.
EC panic is not covered by the standard (0-F) ACPI notify values.
Arbitrarily choosing B0 notify, which is in the 84-BF device specific
ACPI notify range.
This will be a no-op until the kernel driver is also updated to handle
this event.
BUG=b:258195448
BRANCH=None
TEST=Observe event with modified cros_ec_lpc driver
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Iafa642c1c50f9a0083a8e618e1eabec9a7ce39b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69391
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DTTS is Dynamic Thermal Table Switching Proposal.
DTTS needs one bit to save the body detection result from EC.
Define mode change STTB bit for Desktop (1) and laptop (0).
This bit is Switch thermal table by body detection status.
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PS2K device needs to be under PCI0, not LPCB, for Windows to
recognize it. Same change was made to ChromeEC previously.
Test: Boot Win11 on Drallion, verify built-in keyboard functional.
Change-Id: I12019592dfa1d869ba57c1ff6c25ac6bdeb7a300
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This reverts commit 672bd9bee5.
Reason for revert: Gmeet resolution dropped. When system starts
Gmeet video call, it uses the hardware accelerated encoder as per
the expectation. But, as soon as another system connects to the call,
the immediate fallback observed from hardware to software encoder.
Due to this, Gmeet resolution dropped from 720p to 180p.
Currently, this issue observed on AlderLake-N SoC based fanless
platforms. This issue is not seen on fan based systems.
BUG=b:246535768,b:235254828
BRANCH=None
TEST=Built and tested on Alderlake-N systems. With this revert
Gmeet resolution drop not observed.
Change-Id: Idaeaeaed47be44166a7cba9a0a1fac50d2688e50
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Set _STA to 0xB for GOOG000C/GOOG000E devices to prevent showing
as missing drivers under Windows.
Change-Id: I0887fd6e18528d2c8523e7bc66db9efaa31adf5d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68462
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Several EC host commands check for support of a given feature or msg
version, and a non-zero response does not necessarily indicate an actual
error. Since the caller is (should be) handling the non-zero response to
the host command, demote the EC printk from ERR to SPEW to clean up the
console log and prevent non-errors from causing false failures in
firmware tests.
BUG=b:238961053
Change-Id: Ib7afc0b7e5b571acb56252f7adb518a6b2716b62
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68259
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since mono_time is now 64-bit, the utility functions interfacing with
mono_time should also be 64-bit so precision isn't lost.
Fixed build errors related to printing the now int64_t result of
stopwatch_duration_[m|u]secs in various places.
BUG=b:237082996
BRANCH=All
TEST=Boot dewatt
Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
In order to fix the USB port of type-C dongle has no function after
reboot/shutdown, modify ufp which is in google_chromeec_usb_pd_get_info
from the bit1 of type-c role (PD_CTRL_RESP_ROLE_DATA).
BUG=b:239138412
TEST=Built coreboot image and verified that using this patch can detect
usb drive after reboot.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I73a4a6ec37129388783599125f067068d155d93f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67168
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add multiple fan support for dptf policies
BUG=b:235254828
BRANCH=None
TEST=Built and tested on Redrix system for two fans
Change-Id: I96ead90e3b805bd20de03e4bef4fa4b9fbaaaedd
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Compile-time support of DPTC is controlled by
EC_ENABLE_AMD_DPTC_SUPPORT in each variant's ec.h file. This CL removes
EC_ENABLE_AMD_DPTC_SUPPORT and replaces it with the Kconfig value
SOC_AMD_COMMON_BLOCK_ACPI_DPTC.
Each variant's run-time support of DPTC continues to be controlled by
the variant's overridetree.cb "dptc_enable" value.
BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Boot skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ic101e74bab88e20be0cb5aaf66e4349baa1432e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
PNOT() should be called when the battery status changes, to give the SOC
an opportunity to handle it. This is in preparation for the low/no
battery boot changes.
This CL also updates the PNOT() comments to better match the name of the
function and why it's called.
BRANCH=none
BUG=b:217911928
TEST=Boot skyrim
Change-Id: I8b74313d242fd4959315a67579eb6c5f49a31a76
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66993
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
The agah EC code will monitor adapter current to choose corresponding
DPTF oem variable table. When it changes, this event will send to the
ACPI FW through host event and then pass onto the DPTF kernel driver.
This patch adds support for that feature.
BUG=b:238921409
TEST=add Printf() calls to the ACPI,
and check these Printf() will show up in the kernel log
when EC send oem variable table change notify.
Change-Id: I1dbbfd9b3d65b56d77050c9ba9957e54530c3a0e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66574
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DPTF power participant device needs to be notified when power
source changes so it can re-evaluate power source and power source
change count, this can be later used by DPTF along with methods
provided by EC.
Corresponding changes in EC are https://crrev.com/c/3545778 and
https://crrev.com/c/3547317
BUG=b:205928013
TEST=Build, boot brya0 and dump DSDT to check change
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I07f58b928a0dba92bec3817177142c586e5014b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
The flag EC_BATT_FLAG_CUT_OFF was added with the CL:
3704470: battery: Set battery cutoff flag
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3704470
This flag is set in the ACPI memory mapped area when the command
`ectool batterycutoff` is issued so ACPI code can respond
appriopriately. This CL adds the flags to coreboot ACPI.
BRANCH=none
BUG=b:217911928
TEST=Boot nipperkin with low & no battery
TEST=Boot skyrim with low & no battery
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I4e63ff4fc2d6b0ecf767a6bffd81f823c74c15bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66803
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since there are many identifiers whose name contain "__unused" in
headers of musl libc, introducing a macro which expands "__unused" to
the source of a util may have disastrous effect during its compiling
under a musl-based platform.
However, it is hard to detect musl at build time as musl is notorious
for having explicitly been refusing to add a macro like "__MUSL__" to
announce its own presence.
Using __always_unused and __maybe_unused for everything may be a good
idea. This is how it works in the Linux kernel, so that would at least
make us match some other standard rather than doing our own thing
(especially since the other compiler.h shorthand macros are also
inspired by Linux).
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
There is a new field in EC EMEM for arbitrary GPU data to be passed
from EC to ACPI FW; this patch adds support for it.
Also the current host event for _Q0C (EC_HOST_EVENT_USB_CHARGER) is
unused, and is being repurposed in the next CL, so this patch drops
the handler.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iff6f935a5bdc8c47277eaa6bcbedd5fc5ed311a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65485
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This change copies ec_commands.h directly from the ChromiumOS EC repo,
with the exception of changing the copyright header to SDPX format.
Update to commit SHA1 2cbf6fbf (ec_commands: Drop VBNV read/write
support).
BUG=b:178689388
TEST=none
BRANCH=none
Change-Id: I74fa8b1171ca109dee163a7657659cdac1687450
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65469
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With CB:65012, google_chromeec_vbnv_context() is no longer used. Remove
it from the codebase.
BUG=b:178689388
TEST=./util/abuild/abuild -t GOOGLE_STOUT -a -x
Change-Id: I717f600f0f73c3ca932b6a442a9d5b90c35c8f3b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
These changes made my crude pattern matching work with
coccinelle simpler.
Change-Id: I83f3ef38b8663640594b4d726838f7a6f96a58a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
On some systems, the Chrome EC controls both the USB Type-C mux as well
as the retimer. Introduce a boolean property "mode-switch" to denote
switches which act as a mode-switch.
BUG=b:235834631
TEST=None
BRANCH=None
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Change-Id: If209a8529ff7ec424f23fd96875ac95a1fe6267d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add fan speed rpm control for DPTF based Active2 policy as per
document #626708, by utilizing existing FAN0 variable from
src/ec/google/chromeec/acpi/emem.asl#18.
There is no corresponding EC change required for this policy
support because EC fan code already exporting this rpm value
using EC_MEMMAP_FAN for FAN0.
BUG=b:224457192
BRANCH=None
TEST=Built and booted on ADL-P based Brya system and
verify the fan speed in rpm under sysfs path
cat /sys/bus/acpi/devices/INTC1048\:00/fan_speed_rpm.
Change-Id: Ibb1646b1fb1659fd853ece97d97bb9dee2a3f57e
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Some platforms have retimers which can be configured via the EC. Add a
handle to these retimer devices to the Type C connector device, using
devicetree references.
BUG=b:208883648
TEST=Verify disassembled SSDT on brya.
BRANCH=None
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
If set OEM string as "", it shows "Not Specified" with dmidecode.
Use default string if it is empty.
BUG=b:230039300
TEST=set OEM string "" and show google with dmidecode -t 2.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I097e1be696ae974aadc47feb8d0c1dae672a5c82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.
Change-Id: Ief40e790fdee336fd6c786e18cd01c41fa658c2c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
In most boards, it doesn't write OEM_NAME in CBI to override the
manufacturer name in the SMBIOS table. It' better use the "BIOS_INFO" than "BIOS_ERR"
BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I52eb1e6926eaac30b1dbee13ab750ef15b466d89
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently, many Linux drivers use DMI quirks to identify ChromeOS
devices and handle them accordingly: namely they look for the SMBIOS
system manufactuer to be "GOOGLE" or "Google", and the bios-vendor to be
coreboot. Historically this was consistently the case, but recent model
ChromeOS devices allow the OEM to set the mainboard manufacturer, which
is also the default system manufacturer. This breaks many DMI quirks,
notably ones used by SOF (sound open firmware) for audio.
To fix this, set the system manufactuer for ChromeOS devices to "Google"
for devices selecting CONFIG_EC_GOOGLE_CHROMEEC_SKUID, leaving the OEM
customization in place for the mainboard manufacturer. Since boards
selecting CONFIG_EC_GOOGLE_CHROMEEC_SKUID are the only ones overriding
the default mainboard manufacturer, they are the only ones which need
this correction.
Test: build/boot google/bloog with Linux 5.16, verify SOF drivers
correctly detect device as a Chromebook and load the appropriate
audio firmware.
Change-Id: I9de17fa12689ab4e627b995818aa3d2653102b04
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62796
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support of MENU key (aka hamburger) for Chromebooks with Vivaldi
keyboard
BUG=b:215038215
TEST=manually tested on Anahera device: pressing T13 key opens menu
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I07873dd9385c743a6512408688ec44a5e97219f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61835
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change copies ec_commands.h directly from the Chromium OS EC repo,
with the exception of changing the copyright header to SPDX format.
Update to commit hash af9a119
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I1f2a140257d6127fb19bb514bc345466247b7499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Clang does not seem to work with 'fall through' in comments.
Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Now that the console system itself will clearly differentiate loglevels,
it is no longer necessary to explicitly add "ERROR: " in front of every
BIOS_ERR message to help it stand out more (and allow automated tooling
to grep for it). Removing all these extra .rodata characters should save
us a nice little amount of binary size.
This patch was created by running
find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';'
and doing some cursory review/cleanup on the result. Then doing the same
thing for BIOS_WARN with
's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi'
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Currently only PLD group is used to check USB port number. In the
future, we want to use custom PLD fields, so custom PLD should also be
considered when checking USB port number.
BUG=b:216376040
TEST=emerge-brya coreboot & SSDT dump in Brya test device
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Id8076a2a952de61a6f38fbdecd76e991487bf696
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
