Commit graph

4 commits

Author SHA1 Message Date
Maximilian Brune
2efe4df522 treewide: Assume FMAP_SECTION_FLASH_START = 0
Now that we require the FMAP to start at offset 0 in the flash, we can
assume this across the entire codebase and therefore simplify it on
several ends.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ieb1a23f9c0ae8c0e1c91287d7eb6f7f0abbf0c2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86771
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2025-04-18 14:57:05 +00:00
Arthur Heymans
a7eb390796 mb/*/*/*.fmd: Start flash at 0
FMAP should not contain information about the memory map.

Done with the following command:
"find -name \*.fmd -exec sed -i 's/\(FLASH\).* \(.*\) /\1 \2 /' {} \;"

for AMD:
All addresses that amdfwtool expects as command line parameter have the
ADDR_REL_BIOS (flash address) address_mode setting. One exception is
the *_FW_A_POSITION and *_FW_B_POSITION addresses. But amdfwtool checks
if memory or flash addresses are passed and converts accordingly. So
changing the address from memory -> flash doesn't matter for the
resulting binary.
Since commit 41a162b7a8 ("soc/amd/phoenix/Makefile.inc: Pass APOB_NV
address as offset") and therefore since phoenix SOC, APOB_NV is passed
as flash offset. But before that the memory ABL always assumed a MMIO
address (no matter the address_mode) so we need to add a little quirk
for that.

tested: boot glinda based mainboard and also check that memory training
is still cached successfully in APOB_NV.

Change-Id: Iac86ef9be6b14817a65bf3a7ccb624d205ca3f99
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2025-04-09 17:11:43 +00:00
Felix Held
f9af266189 util/amdfwtool: add support to specify RPMC NVRAM region
Add support to specify the base and size of the replay-protected
monotonic counter (RPMC) non-volatile storage area in the SPI flash. A
later patch will use this to tell amdfwtool about the location and size
of the corresponding FMAP section.

This code is ported from
github.com/teslamotors/coreboot/tree/tesla-4.12-amd

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idafa7d9bf64125bcabd9b47e77147bcffee739e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83812
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-08 17:41:09 +00:00
Zheng Bao
e35c502a57 amdfwtool: Move code related to getting options to a new file
Cleanup the messy code. The code left in main is all about filling
tables.

To help to do this,
1. Some local variables are put into global struct.
2. Add some functions. Set some functions to global.

TEST=Identical test on all AMD platforms

Change-Id: Ia25c3fd5de7ae48054359f0f6551d91d7a4f6828
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-06 11:05:07 +00:00