This properly supports power_on_after_fail setting on affected
mainboards.
Tested on GA-H61M-S2PV
Change-Id: I3dcc4f032bc5f629fb916c4122beb8dc096bab20
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since a generic ITE GPIO driver is available and in use, the existence
of chips-specific drivers no longer make sense. Remove the dead code
in favor of generic GPIO driver.
Change-Id: I7e031d12192af4bd47923d87c1d02c64f9c851a2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83497
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enables the driver for ITE SIOs supporting the GPIO register layout
(confirmed with datasheets for the modified ITE SIO Kconfigs, SIOs
with unavailable datasheets are unmodified).
Other ITE SIOs may select it with SUPERIO_ITE_COMMON_GPIO_PRE_RAM
and must then provide the number of GPIO sets specific to a chip
via SUPERIO_ITE_COMMON_NUM_GPIO_SETS.
Change-Id: I0868ff3e9022b135c21f4c1a6746d6440b8f0798
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a generic driver to configure GPIOs and LEDs on common ITE
SuperIOs. The driver supports most ITE SuperIOs, except Embedded
Controllers. The driver allows configuring every GPIO property
with pin granularity.
Verified against datasheets of all ITE SIOs currently supported by
coreboot, except IT8721F (assumed to be the same as IT8720F),
IT8623E and IT8629E.
Change-Id: If610d2809b56c63444c3406c26fad412c94136a5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83355
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Based on the non-public "ITE IT8659E-I Preliminary Specification V0.7.2
(For H Version)".
TEST=Initialize IT8659E on the new Protectli platform
Change-Id: I11657ec6e1c880f0cee247071486a904a92bb7a1
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
A function to disable the PME# output was added. This is required to
set up the SuperIO on the "HP Pro 3500 Series" mb.
Change-Id: I94f023ba6eb24b5fb1c5e0b30eb65738f50a87eb
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81589
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The 3VSBSW# signal can now also be disabled again which is necessary to
power components down properly in SMM when entering S5. In such cases
the signal will be enabled only in the SMM S3 handler.
Change-Id: I8535176908ec39e9916774135e028cbc7c203474
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81588
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
A number of ITE SIOs support "special fan control vectors", which
effectively allow non-linear fan speed control. This is for example used
by the vendor firmware of the "HP Pro 3500 Series".
The special vector registers won't be written to until the mb's
devicetree configures `FAN_VECX.tmp_start != 0`.
Change-Id: I93df2b5652fc3fde775b6161fa5bebc4a34d5e94
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The it8772f is now configured by the much better common code that is
used for other chips in the family as well. This mainly concerns the EC,
the GPIO functionality was not moved to common as it currently lacks a
sane abstraction in any codebase.
The datasheets of the it8772e(f) and it8728f (for reference) were
studied and verified against the common code, adding exceptions where
needed.
Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81310
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add Kconfig option for full-speed setting. Some variants do not support
the full-speed at limit configuration (IT8772F). Keep it enabled for all
current variants that use the common EC code as it was previously
enabled unconditionally - datasheets weren't revisited individually.
Change-Id: Icf24ea1c4f41771a18803957456f0aeba0e51b13
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81525
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix warning for disabled thermal inputs.
Fix warning for PECI thermal inputs if one was set up previously.
Depending on the mb, the superio will not go through power-on reset and
retain its registers. Do not trigger a warning if the current register
value aligns with the desired value. Don't return early if some input is
already configured for PECI, simply overwrite the configuration.
Both warnings were observed while porting the "HP Pro 3500 Series" mb.
Change-Id: Ibabe1b1ef55f2acb2074eceb535ec684bffc8155
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some LDNs do not implement the activate bit at all, e.g. ITE GPIO LDNs
are an example where the LDN is always active. The pnp_generic.asl can
be used to describe the GPIO LDN resources configured by the platform,
however the register 0x30 is always 0 for these LDNs, so OS will not
claim the reported resource for the GPIO device, because _STA will
return inactive LDN.
Add SUPERIO_PNP_NO_DIS macro to generate _STA method returning an
always active LDN and skip _DIS generation. Define the SUPERIO_PNP_NO_DIS
for SIOs which use the pnp_generic.asl preserving the previous states,
except the ITE GPIO LDNs.
Change-Id: Ieb827fdffe7660b875cba6ca99b0560b4cab66b4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80496
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Unfortunately, the datasheet for IT8629E is not public. Therefore, we
will use the functionally closest chip (i.e. IT8728F) as a reference
and try to reverse-engineer where necessary.
IT8629E seems to be very similar to IT8628E (again, no public
datasheets), as the chip id is 0x8628.
Known differences:
- LDN 0x08 (functionality is unknown)
- Supports 6 fans
Change-Id: I44d0377da11f0e118017caa4357012df9373b322
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80344
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Macros can be confusing on their own; hiding commas make things worse.
This can sometimes be downright misleading. A "good" example would be
the code in soc/intel/xeon_sp/spr/chip.c:
CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev,
This appears as CHIP_NAME() being some struct when in fact these are
defining 2 separate members of the same struct.
It was decided to remove this macro altogether, as it does not do
anything special and incurs a maintenance burden.
Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I41191f6971bdd8ecff2c56f4bfa2b57c87530b83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80076
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The fixed I/O resource descriptor macro implies that the device will
only decode 10 of the 16 IO port bits causing aliasing. Use an I/O port
descriptor instead and use Decode16 to tell the OS that this I/O
resource will decode all I/O address bits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6183d625fb7968fb33caf396f19feef8917ba4fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
IT8784E is basically a IT8786E stripped from serial ports 3-6.
The patch creates a chip directory for IT8784E used by
protectli/vault_cml platforms.
TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the
configuration with superiotool and compare the configuration with
proprietary firmware.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibe01358611f3ce3f155ddb01a7d177a3ff75765e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
_PRS only makes sense if _SRS is implemented.
Change-Id: I030bd716215b5ac5738e00ebf6ed991d9d6c5ca0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69513
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Set the watchdog timeout to 0 in ite_kill_watchdog, as in some ITE
models it is set to non-zero by default, activating the watchdog despite
us setting the control register to 0.
Based on:
- "ITE IT8786E-I Preliminary Specification V0.4.1 (For D Version)"
- Linux it87_wdt driver
Change-Id: I1e78e2acc96e9dd0f283c5c674d3277d26cdee26
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The `find_resource` function will never return null (will die instead).
In cases where the existing code already accounts for null pointers, it
is better to use `probe_resource` instead, which returns a null pointer
instead of dying.
Change-Id: Ic6e28add78f686fc9ab4556eddbedf7828fba9ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.
Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Some chips can read external temperature sensor values only to TMPIN3.
These use EC register 0x55, bit 7 to enable that. This patch adds
support for this. It is called "old PECI" by lm_sensors [0].
Other chips can read to any TMPIN[1-3] which is configured in EC
register 0x51 like the other temperature sources. This was the only
supported method. This patch adds a Kconfig option to indicate this
variant.
This patch was tested on an Acer Aspire M3800 which has an IT8720F that
reads the CPU temperature via PECI. It allows the automatic fan control
feature of the Super I/O to work.
Overview of support per chip in the coreboot tree, determined from
reading the publicly available datasheets or lm_sensors, if noted:
Old PECI:
* IT8718F
* IT8720F
* IT8781F, IT8782F, IT8783E/F
Normal PECI:
* IT8721F (exception: no PECI to TMPIN2)
* IT8728F
* IT8772E (uses separate code in coreboot, not superio/ite/common)
* IT8786E
* IT8613E, IT8623E (lm_sensors)
[0] Linux kernel 5.4.48, drivers/hwmon/it87.c
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: Iab7115852437d46c9b1269bba61ffcf680fe5a6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
According to the IT8728F datasheet it is possible to add an extra delay
between 3VSBSW# being set and PWRGD3 being set during resume from
Suspend-to-RAM. This is enabled in the special function selection
register, the default being 0.
This is also useful for the IT8720F although this chip does not have the
PWRGD3 output. On the corresponding pin it has PWROK2, which the setting
then seems to apply to.
The datasheet for the IT8720F marks the corresponding bit as reserved,
but the vendor BIOS of an Acer Aspire M3800 sets it anyway. Without
setting the bit, coreboot fails to resume from S3. Oscilloscope
measurements have shown that setting the bit increases the delay between
3VSBSW# being set and PWROK2 being set from around 1 us to 140 ms. The
actual use of PWROK2 on the board design is unclear - the only
destination it seems to reach is a pin header near the SuperIO marked as
"GPIO1".
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I51cbf2470dc2b840a647a20090acb5a0cf4f4025
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Per the datasheet and the it87 kernel driver, the IT8728F supports
both 5 fans (vs 3) and use of a single 7-bit register for the
PWM slope (5 bits in closed-loop mode).
Change-Id: I3d1e6f5030f18d2c8ff533965ae4718be0f3c279
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add support for tachometer closed loop mode, and programming
of initial RPM vs initial PWM value.
Change-Id: Idff29331c979f8518021103b6f8d19e75e657e3a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The interface selection register of the environment controller (EC)
gives the choice between "Internal generated 32 MHz" and "24 MHz" for
the "SST/PECI Host Controller Clock Selection".
Previously the chip was always configured for the 32 MHz clock. Add an
option that can be set from devicetree.cb to allow using the 24 MHz
clock.
Without this setting the automatic fan control on an Acer Aspire M3800
was slow to respond to temperature changes.
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: Ib2bce10a828fb4a7d837f6c5f5b1d00cc51be0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44166
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This applies to the automatic fan control mode of the environment
controller (EC). Previously the affected bit was always cleared while
the default value is 1 according to datasheets. Add a variable that can
be set per mainboard in devicetree.cb.
In the IT8783E datasheet that bit is marked as reserved.
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: Ie74102ac0d54be33558c161c9c84594d121772b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This Super I/O was not being built at all. Correct that.
Change-Id: Id053fa919cac7b2df6a6fc45aae5e34a0dc8c0ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The authors from the header of the files are added in a previous commit.
Change-Id: Iafeaafb9689c65bd2f5de3960097ec0d4c1009e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38544
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Long-term plan is to support loading runtime configuration
from SPI flash as an alternative, so move these prototypes
outside pc80/.
Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These SIOs are not being used or tested by abuild, so remove them from the
tree. The only 3 currently unused SIOs that don't get removed here have board
ports in review.
src/superio/fintek/f71805f
src/superio/fintek/f71872
src/superio/intel/i8900
src/superio/ite/it8671f
src/superio/ite/it8716f
src/superio/nsc/pc87309
src/superio/nsc/pc87360
src/superio/nsc/pc87366
src/superio/nsc/pc97317
src/superio/smsc/dme1737
src/superio/smsc/lpc47b272
src/superio/smsc/lpc47b397
src/superio/smsc/sch4037
src/superio/smsc/sio1036
src/superio/via/vt1211
src/superio/winbond/w83697hf
src/superio/winbond/wpcd376i
Signed-off-by: Martin Roth <martin@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I61d486d2c1e2b85eb292eaa78316c36e1735ebf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
