The headers added are generated as per FSP v3361.03
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:247855492
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: I267a0aefca18492bcbcfbf7acbe271887f0a39cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Add the headers for 2.2.3.1, which includes the following changes
over 2.2.0.0:
• [Implemented]GLK: XHCLKGTEN Register setting causes S0ix entry
failure in less than 5 cycles when a USB2 Ethernet Dongle is
connected. Refer GLK BIOS Spec Volume1 CDI# 571118 under chapter
7.20.6 for new Register settings.
• [Implemented] [GLK/GLK-R] DDR4 16Gb SDP Memory support for Gemini
Lake/Gemini Lake – R
• [Update] MRC new version update to 1.38.
• [Fixed][GLK-R][WLAN] Removed the DSW function - Wake on LAN from
S4 issue with latest Wifi driver.
[Update] MRC new version update to 1.39. Included fix for
MinRefRate2xEnable and support for Rowhammer mitigation.
• [Fixed] Disable Dynamic DiffAmp and set CTLE from 7 to 5. This
change specific to DDR4 memory configuration.
• GLK Klocwork Fix
• [Update] MRC new version update to 1.40.
Added in a separate directory as the default. The 2.2.0.0 headers
were left and will be used for Google boards, as some offsets have
moved.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I09498368b116c2add816eeada2fa4d0dba6e5765
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The headers added are generated as per FSP v3301.03
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:243693364
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: Idbd39ed53d4ba05248a0e83c104846960253931e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The headers added are generated as per FSP v3257_00_40.
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:238791453
BRANCH=firmware-brya-14505.B
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: If8fd6700f0afed7e2bd5d73a95407dbfd3e88abd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch fixes a missing header file compilation issue when coreboot
selects MP_SERVICES_PPI_V2 config from MTL SoC.
The `MpServices2.h` file doesn't exist in the upstreamed EDK2 repo
(integrated with `edk2-stable202111` stable tag).
Currently MpServices2.h file is being copied from the
`edk2_stable202005` stable tag.
BUG=b:237960384 ([Intel FSP][EDK2011] MpServices2.h header is missing
in upstream EDKII git)
TEST=Able to fix the compilation issue on Google/Rex (Meteor Lake)
when MP_SERVICES_PPI_V2 kconfig is enabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib7c406ff51439c93c6d15f3a69808b4d1590cfa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65624
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update header files for FSP for Meteor Lake platform to version 2222_01, previous version being 2173_00.
FSPM:
Includes below 2 UPDs
1. TdcEnable
2. TdcTimeWindow
FSPS:
Address Offset changes.
BUG=b:234701164
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I529118c35fa9f851ee2b5f23712ac70e2a5b53c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64878
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
The headers added are generated as per FSP v3172
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I5aa0611b19bb4f6667a95d2539cc2d17de6dcf07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The headers added are generated as per FSP v3127_05_8.
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I9dd14468ec09bfe1a0904686e66d37a7389efdd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Revert CdClock setting and use default value 0xff.
Previous problem was fixed by Jasperlake FSP in version 1.3.09.31,
so we can use the original CdClock setting in baseboard.
BUG=b:206557434
BRANCH=dedede
TEST="Built and verified on magolor platform to confirm FSP solution works"
Cq-Depend: chrome-internal:4662167
Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The headers are now unused, drop them.
Change-Id: Ibfaa3029ddc614935481ce736c9d971bf4831b5d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
Change request here:https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
BUG=b:200113959
TEST=Verified on Meteor Lake platform, without any compilation error
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1f33db43f7932cf6d165d0c70a0e2922dad00a09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The headers added are generated as per Alder Lake N FSP v2503_00.
Changes include:
- Add all header files for Alder Lake N FSP.
- List of header files: FirmwareVersionInfoHob.h, FspmUpd.h, FspsUpd.h,
FspUpd.h, MemInfoHob.h
- Select FSP_HEADER_PATH
BUG=b:213828776
BRANCH=None
Change-Id: I97afa6d47cc825703a8dc82216250bfc5e09dc9b
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
The headers added are generated as per FSP v2511_04
Previous FSP version was v2471_02
Changes include:
- UPDs description update in FspsUpd.h and FspmUpd.h
- Adjust UPD Offset in FspmUpd.h
- Name change of UPDs in FspmUpd.h and FspsUpd.h
- Copyright year is updated in FspmUpd.h and FspsUpd.h
- Updated spd_upds and dq_upds structure variables in meminit.c
- Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask
in fsp_params.c
BUG=b:213959910
BRANCH=None
TEST=Build and boot brya
Cq-Depend: chrome-internal:4448696, chrome-internal:4445910
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>
Change-Id: I39646c6812afbf622171361b8206daeacdaafac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Elkhart Lake was hooked up to the FSP repo with commit 79fcadb3c4
(soc/intel/elkhartlake: Use FSP from FSP repo by default) making
these headers obsolete. Thus, drop them.
Change-Id: I2d6a4d4614ae21d5b8e77eceb85baa13e491c2ae
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add a devicetree setting to configure the CdClock (Core Display Clock)
frequency through a FSP UPD. Because the value for this UPD's default
setting is non-zero and devicetree settings default to 0 if not set,
adapt the devicetree values so that the value for the UPD's default
setting is used when the devicetree setting is zero.
Also update the comment describing the FSP UPD in the header file
FspsUpd.h to match the correct CdClock definition.
BUG=b:206557434
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit ae0ea32c52.
This change should not have merged until the 2471_02 FSP change is ready
for merge.
BUG=b:211481222
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot brya0
to kernel.
Change-Id: Iae5b0c53ace196053e1e155efd2e08f438979ba7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The headers added are generated as per FSP v2471_02.
Previous FSP version was v2422_01.
Changes Include:
- UPDs description update in FspsUpd.h
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
BUG=b:208336249
BRANCH=None
TEST=Build and boot brya
Change-Id: I4d04652c06a1c1823d3859be209710c273a2ae8c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch includes (edk2/edk2-stable202111) all required
headers for edk2-stable202111 EDK2 tag from EDK2 github
project using below command:
>> git clone -b edk2-stable202111 https://github.com/tianocore/edk2.git
commit hash: bb1bba3d776733c41dbfa2d1dc0fe234819a79f2
Only include necessary header files.
MdePkg/Include/Base.h was updated to avoid compilation errors
through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE.
Note: edk2-stable202111 tag is required to adopt FSP 2.3 specification.
- Need to add ExtendedImageRevision in FSP_INFO_HEADER structure.
- Need to add FSP_NON_VOLATILE_STORAGE_HOB2 header.
Change-Id: I786cc05f9a638ac6226ebc8c0eaf1dc8189a4ca4
Signed-off-by: Subrata Banik <subi.banik@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
coreboot code currently supports different UDK binding as per
underlying FSP requirement, example: ICL and TGL uses
UDK_2017_BINDING while ADL uses UDK_202005_BINDING Kconfig.
These UDK binding Kconfigs are being used to choose the correct
UDK_VERSION.
This patch introduces `UDK_BASE` Kconfig option so UDK_VERSION
if clause don't need to add specific UDK binding Kconfig everytime with
introduction of newer UDK bindings in future.
Tested with BUILD_TIMELESS=1, Hatch remains identical.
Change-Id: I64c51aa06a14f0ce541537363870ac3925b79a68
Signed-off-by: Subrata Banik <subi.banik@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The headers added are generated as per FSP v2374_01.
Previous FSP version was v2347_00.
Changes Include:
- Offset change in FspmUpd.h and FspsUpd.h
BUG=b:201239436
BRANCH=None
TEST=Build and boot brya
Cq-Depend: chrome-internal:4150766
Change-Id: I097e854bcb4033bdaf2498fb97b255e87d3dd70f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57920
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some headers in vendorcode are still needed but the UPD definitions
can be taken from the FSP repo.
Change-Id: I7bb96649ecba9d313cfce50af202aabcf610680f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
coreboot expects different names for FSP UPDs so use some CPP to make
it happy.
Change-Id: I4b2c2dd6ba40cb58bc2089eb9204fd4f70b037aa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Sync the MemInfoHob.h with current FSP code.
BUG=b:190339677
TEST=dmidecode -t 17 can show the memory information.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I80d1252b1f12b164d4f6d3a01221507cdfbe4d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
The headers added are generated as per FSP v2237_00.
Previous FSP version was v2207_01.
Changes Include:
- Add VccInAuxImonIccImax in FspsUpd.h
- Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h
BUG=b:192199787
BRANCH=None
TEST=Build and boot brya
Change-Id: Ie291204a3fa0b9451c418c84bd40a17ef08a436c
Cq-Depend:chrome-internal:3970327,chrome-internal:3925290
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55896
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FirmwareVersionInfoHob.h is removed in JSL FSP v2376 so
remove it from Jasper Lake vendorcode.
BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patch in relation chain
and verify the version output prints no junk data observed.
couple of lines from logs are as below.
Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1
Change-Id: Iad0429630665f50dbc1541487c9061dd1a19907c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45908
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update MdePkg/Include/IndustryStandard/SmBios.h to avoid compilation
errors through safeguarding definitions with DISPLAY_FSP_VERSION_INFO_2
Kconfig.
BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patches in relation chain
and verify the version output prints no junk data observed.
Couple of lines from logs are as below.
Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1
Change-Id: I9698861be1f969ddca7f171767a54ac486502c74
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45906
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sync the MemInfoHob.h with current FSP code.
BUG=b:190339677
TEST=dmidecode -t 17 can show the memory information.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifd3e6a264131437c67d17ec80f37f5e8d0a03a79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update FSP headers for Tiger Lake platform generated based on FSP
version 4133 to include post PRQ UPDs.
BUG=b:188452018
BRANCH=none
TEST=build voxel
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54811
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FSP-M/S/T related headers added are generated as per FSP v3162.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ie6e6db704bcf86034fc9a3423101f0391ba2327e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54869
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The headers added are generated as per FSP v2162_00.
Previous FSP version was v2117_00.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Remove DisableDimmMc*Ch* Upds in FspmUpd.h
- Add DisableMc*Ch* Upds in FspmUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h
Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid
compilation failure other change related to UPDs name change will be
part of next patch in relation chain.
BUG=b:187189546
BRANCH=None
TEST=Build and boot ADLRVP using all the patch in relation chain.
Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e
Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913
Cq-Depend: chromium:TODO
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54083
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The headers added are generated as per FSP v2117_00.
Previous FSP version was v2081_02.
Changes Include:
- Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h
- Remove FivrFaults and FivrEfficiency Upds from FspmUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h
BUG=b:184129128
BRANCH=None
TEST=Build and boot ADLRVP
Change-Id: I068552084b1ef3e5c4fba7a46240d116c92c7b5b
Cq-Depend: TBD
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update FSP headers for Tiger Lake platform generated based on FSP
version 4133. Previous version was 4043.
BUG=b:185463045
BRANCH=none
TEST=build and boot voxel
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I27d8f7783a944bdd21e3615799b1342ffb0edd22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
