Link .init section near the end of bootblock program.
It contains _start16bit, gdtptr and gdt that must be
addressable from realmode, thus within top 64 KiB.
Change-Id: If7b9737650362ac7cd82685cfdfaf18bd2429238
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
It was confusing to have this defined while there was another
symbol bootblock_protected_mode_entry that was not really used
as an entry point.
Change-Id: I3da07ba9c0a9fc15b1515452adfb27f963659951
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48404
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCI0 MMIO window was defined between TOM and 4 GiB. This was
overlapping with the FCH MMIO devices. The first MMIO device after TOM
is the FCH IOAPIC.
This wasn't causing a problem for linux other than the fact that
/proc/iomem showed all the MMIO devices under the PCI root bridge.
On Windows this was causing all the MMIO devices to have conflicting
resource errors.
BUG=b:175146875
BRANCH=zork
TEST=Boot linux and verify peripherals all work. Boot windows and
verify the i2c controllers show up. The GPIO controller still has a
problem related to power.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idc409f1318e6da5a693ccbb3da74aafd13f1e058
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49853
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Zork platform was not booting with MCACHE enabled since psp_verstage
had following issues with MCACHE.
Fix all the issues and re-enable MCACHE for Zork.
* psp_verstage should call vboot_run_logic, not verstage_main.
vboot_run_logic calls after_verstage which handles RW MCACHE build.
* It should avoid low-level apis for cbfs access.
cbfs_map will build RO MCACHE if it's the first stage, while other
low-level apis won't.
* It should call update_boot_region before save_buffers
MCACHE should be transferred to x86 so we should build it before
calling save_buffers
BUG=b:177323348
BRANCH=none
TEST=boot Ezkinil
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I08c5f8474600a06e3a08358733a38f70787e944a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49468
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is not the correct way to specify the FixedDMA devices. I'm
removing for now since it adds confusion.
BUG=none
BRANCH=zork
TEST=Boot zork to linux and make sure UART still works
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I17b9c8dbe4f9c4b64ee1bd69cb9b30998e727632
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The default case is only needed to make the compiler happy.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idf54e7128f9e9d96f15ac7ab121f22621e033fac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49941
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The empty string causes an undetectable build error.
Filter out the board which doesn't define this variable.
A great odds that the reason is the board doesn't set a
valid ROM size.
Change-Id: Iade1961460285acdec245c553c7b84014c30c267
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to
generate SPD files for currently known LP4x memory parts that can be
used with ADL-based mainboards.
BUG=b:176491791
Change-Id: Ie75e43833bf9ba6557fc59cf8b4a0358d495e56a
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49919
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In ./include/device/device.h, the struct device_operations is defined
as below.
------------------------------------
#if CONFIG(HAVE_ACPI_TABLES)
unsigned long (*write_acpi_tables)(const struct device *dev,
unsigned long start, struct acpi_rsdp *rsdp);
void (*acpi_fill_ssdt)(const struct device *dev);
void (*acpi_inject_dsdt)(const struct device *dev);
const char *(*acpi_name)(const struct device *dev);
/* Returns the optional _HID (Hardware ID) */
const char *(*acpi_hid)(const struct device *dev);
#endif
------------------------------------
So we also need to add the same #if in the C source.
Change-Id: I488eceacb260ebe091495cdc3448c931cc4a1ae3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Use the same variable name as soc/intel to implement a common
_PIC method at top-level ASL.
Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Remove typedef device_nvs_t and move struct device_nvs
outside of global_nvs. Also remove padding and the reserve
for chromeos_acpi_t.
Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
As a result of S3 resume, call ALIB function 1 to report the current
AC/DC state.
BUG=177377069
TEST=Verify printf is called during resume on Morphius
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I3e52b0625c1222f10ea27568d5431328131a26a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The comment doesn't apply to Stoneyridge, Picasso and Cezanne which are
the only SoCs selecting SOC_AMD_COMMON_BLOCK_SMBUS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9024de9d3731a0bc64365f959142bf657a53e193
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Cezanne doesn't have eSPIx00034 register define in PPR. Currently only
Picasso need this option.
Change-Id: Icb8e8a1a59393849395125108bfaa884839ce10f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the soc ACPI _CST table.
The table may be customized to support the different state
combinations and set by the mainboard config.
Tested on deltalake with acpi_idle driver.
Note, intel_idle may not use ACPI _CST table.
Change-Id: I359daa9556edbe263ab0a7f1849c96c8fe1a0da0
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
De-duplicate the MWAIT_RES define. Move it to intel/common/block.
Change-Id: I43903e4f02a549f53101e79f6febd42f2e54f98f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49802
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do not pass ACPI S3 state as a parameter, by locally
calling acpi_is_wakeup_s3() compiler has better chance
for optimizing HAVE_ACPI_RESUME=n case.
Test for acpi_s3_allowed() is already included in the
implementation of acpi_is_wakeup_s3() and is removed
as redunandant.
For ramstage, acpi_is_wakeup_s3() evaluates to
romstage_handoff_if_resume().
Change-Id: I6c1e00ec3d5be9a47b9d911c73965bc0c2b17624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49838
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This matches the _HID used in the picasso UEFI bios.
BUG=none
BRANCH=zork
TEST=boot linux and verify peripherals still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ieb441696cbe67a772632990347c12d1d15cfaf13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is the new _HID that was used for Raven. It matches the _HID used
by the picasso UEFI bios.
This does change the fixed clock used by linux from 133 MHz to 150 MHz.
BUG=none
BRANCH=zork
TEST=boot linux and verify touch screen and touchpad still function
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I37fcb4a4f0148f4843d026902d694c03aeed3c3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is the new _HID that was used for Raven. It matches the _HID used
by the picasso UEFI bios.
BUG=none
BRANCH=zork
TEST=boot linux and verify UART still works
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I138cb445c84997f4a4006cbb4f6617dac25a61b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Change the hardcoded location of microcode patches to using
FIRMWARE_LOCATION.
Change-Id: Iae3d159aa5413a416c54935ab7a809d0f4ff776f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49734
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add UPDs for eDP power sequence adjust
all pwr sequence numbers below are in uint of 4ms.
BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48864
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the old, redundant code for mirroring LPC registers to DMI and make
use of the new common code.
Select the new Kconfig option for LPC DMI mirroring by the option
SOC_INTEL_COMMON_PCH_BASE, which is selected by platforms starting with
SPT, except APL and Xeon-SP. For Xeon-SP, select DMI and the new Kconfig
directly.
APL, even though it's younger than SPT, does not need mirroring.
Test: Set LGMR address by calling `lpc_open_mmio_window` and check that
both the PCI cfg and DMI LGMR register get written correctly.
Tested successfully on clevo/cml-u.
Change-Id: Ibd834f1474d986646bcebb754a17db97831a651f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Starting with SPT, LPC registers IOD, IOE, LGIR* and LGMR need to be
mirrored to their corresponding DMI registers. Add the required writes
to DMI registers, where the PCI config registers get written.
This is already done in soc code for IOD, IOE and LGIR* by mirroring
the registers later, during PCH init. Also the code mostly matches
accross the platforms. This common implementation will avoid delayed
mirroring of the registers and also deduplicate the code.
This change also adds a new Kconfig that will be selected by platforms
requiring mirroring of LPC IO/MMIO registers to their corresponding DMI
registers.
For making use of this common code, the redundant soc code needs to be
dropped and the newly introduced Kconfig option has to be selected. This
is done in the follow-up change.
Change-Id: I39f3bf4c486a1bbc112b2b453381de6da4bbac4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Commit 393992f (cpu/mp_init: Fix microcode lock) fixed the semantics
of parallel loading microcode updates.
So now '*parallel = 1' really means loading MCU in parallel, which
seems to fail inconsistently on around 10% of the APs.
Change-Id: I755dd302abbb58537d840852e8e290bea282a674
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49671
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When MAINBOARD_HAS_SPEAKER is false, the SPKR gets _HID PNP0C02. This
conflicts with the LDRC device. PNP0C02 is also used other places in the
picasso code base, so I chose a random _UID for each device. The _UIDs
are unique in the code base so it's easy to search for duplicates.
BUG=b:175146875
TEST=Boot trembyle to linux
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I01be41515e011293e90a6b42b8e34de8ec3ffc18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
If a _HID/_CID are not unique, we need to add a _UID field to
differentiate the objects.
BUG=b:175146875
BRANCH=zork
TEST=Boot linux, dump ACPI table and verify UIDs are unique
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Icd2ccede2b6c2e332157e2eeca89fba14a46b360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change uses the newly added meminit block driver and updates TGL
SoC and mainboard code accordingly.
TEST=Verified that UPDs are configured correctly with and without this
change.
Change-Id: I6d58cd6568b7bbe03c4e3011b2301209893e85a9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This change adds support for a common block memory driver that can be
used for performing the required operations to read SPD data for
different memory channel DIMMs. This data can then be used by the SoC
code to populate different memory related UPDs.
Most recent Intel platforms follow a similar pattern for configuring
FSP-M UPDs for initializing memory. These platforms use one of the
following topologies:
1. Memory down
2. DIMM modules
3. Mixed
Thus, SPD data is either obtained from CBFS (for memory down topology)
or from on-module EEPROM (for DIMM modules). This SPD data read from
CBFS or EEPROM is then passed into FSP-M using SPD UPDs for different
channels/DIMMs as per the memory organization.
Similarly, DQ/DQS configuration is accepted from mainboard and passed
into FSP-M using UPDs as per the FSP-M/MRC organization of memory
channels.
Different memory technologies on a platform support physical channels
of different widths. Since the data bus width is fixed for a platform,
the number of physical channels is determined by data bus width /
physical channel width. The number of physical channels are different
depending upon the size of physical channel supported by the memory
technology. FSP-M for a platform uses the same set of UPDs for
different memory technologies and aims at providing maximum
flexibility. Thus, the platform code needs to format mainboard inputs
for DQ, DQS and SPD into the UPDs appropriately as per the memory
technology used by the board.
Example: DDR4 on TGL supports 2 physical channels each 64-bit
wide. However, FSP-M UPDs assume channels 16-bit wide. Thus, FSP-M
provides 16 UPDs for SPDs (considering 2 DIMMs per channel and 8
channels with each channel 16-bit wide). Hence, for DDR4, only the SPD
UPDs for MRC channel 0 and 4 are supposed to be used.
This common driver allows the SoC to define the attributes of the
platform:
1. DIMMS_PER_CHANNEL: Maximum DIMMs that are supported per channel by
any memory technology on the platform
2. DATA_BUS_WIDTH: Width of the data bus.
3. MRC_CHANNEL_WIDTH: Width of the channel as used by the MRC to
define UPDs.
In addition to this, the SoC can define different attributes of each
memory technology supported by the platform using `struct
soc_mem_cfg`:
1. Number of physical channels
2. Physical channel to MRC channel mapping
3. Masks for memory down topologies
Using the above information about different memory technologies
supported by the platform and the mainboard configuration for SPD,
the common block memory driver reads SPD data and provides pointers to
this data for each dimm within each channel back to the SoC code. SoC
code can then use this information to configure FSP-M UPDs
accordingly. In addition to that, the common block driver also returns
information about how the channels are populated so that the SoC code
can use this information to expose DQ/DQS information in FSP-M UPDs.
This driver aims at minimizing the effort required for supporting
different memory technologies on any new Intel SoC by reducing per-SoC
effort to a table of configurations rather than having to implement
similar logic for each SoC.
BUG=b:172978729
Change-Id: I256747f0ffc49fb326cd8bc54a6a7b493af139c0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49040
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Creating named objects within a method is highly inefficient. So, pass a
reference to the OperationRegion field that needs to be updated instead.
Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When SerialIO devices are disabled, their _STA method evaluates to 0,
which means the device is not present. It is expected that OSPM would
not attempt to change the power state of a device that is not present.
Lynxpoint does not have these checks, thus remove them from Broadwell.
Also remove the now-unused Arg1 parameter to avoid warnings from IASL.
Change-Id: Ic5e999ac1171ce49db66bec45c58d8aa5711ec53
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
