Switch from passing FSP the serial port address to passing FSP the
serial port output routine. This enables coreboot to use any UART in
the system and also log the FSP output.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16105
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I67d820ea0360a3188480455dd2595be7f2debd5c
Reviewed-on: https://chromium-review.googlesource.com/369116
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add fsp_write_line function which may be called by FSP to output debug
serial data to the console.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16129
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: If7bfcea1af82209dcdc5a9f9f2d9334842c1595e
Reviewed-on: https://chromium-review.googlesource.com/369115
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Add fsp_write_line function which may be called by FSP to output debug
serial data to the console.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16128
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Ib01aef448798e47ac613b38eb20bf25537b9221f
Reviewed-on: https://chromium-review.googlesource.com/369114
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add write line routine which is called indirectly by FSP.
TEST=Build and run on Galileo Gen2.
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16127
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Idefb6e9ebe5a2b614055dabddc1882bfa3bba673
Reviewed-on: https://chromium-review.googlesource.com/369113
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds mainboard_smi_gpi_handler which handles the
SMI event. This can happen in situations like lidclose and
system goes to shutdown.
BUG=chrome-os-partner:54977
BRANCH=None
TEST=When system is in firmware mode executing the command
lidclose from ec console shuts down the system.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15834
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I8ff6001e48dcbbd4cee5097e759352d8fea6189b
Reviewed-on: https://chromium-review.googlesource.com/368948
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
GPIOs which trigger SMIs set the GPIO_SMI_STS status bits in SMI_STS
register. This patch also sets the SMI_EN bit in enable register for
each community based on GPIOROUTSMI bit in gpio pad. When SMI on a
gpio happens status needs to be gathered on gpio number which is done
by reading the GPI_SMI_STS and GPI_SMI_EN registers.
BUG=chrome-os-partner:54977
BRANCH=None
TEST=When system is in firmware mode executing the command
lidclose from ec console shuts down the system.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15833
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id89a526106d1989c2bd3416ab81913e6cf743d17
Reviewed-on: https://chromium-review.googlesource.com/368947
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit 0d9cd92e (chromeos: Clean up elog handling) removed the
individual elog_init() calls from mainboards that did them and automated
adding certain events through the boot state machine. Unfortunately,
the new code would sometimes not log any specific event at all, and
thereby also never call elog_init() (through elog_add_event()) which
adds the "System boot" event.
We can assume that any board that configures the eventlog at all
actually wants to use it, so let's just add another call to elog_init()
to the boot state machine so we can ensure it gets called at least once.
BRANCH=None
BUG=chrome-os-partner:56001
TEST=Booted Kevin, confirmed that eventlog code runs again.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16118
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ibe7bfc94b3e3d11ba881399a39f9915991c89d8c
Reviewed-on: https://chromium-review.googlesource.com/368946
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Instead of relying on global state to determine if an error
occurred provide the ability to know if an add or shrink
operation is successful. Now the call chains report the
error back up the stack and out to the callers.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16104
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id4ed4d93e331f1bf16e038df69ef067446d00102
Reviewed-on: https://chromium-review.googlesource.com/369087
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Don't conditionally compile parts of the code. The unused pieces
get culled by the linker, and the #if's just clutter things up.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16102
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic18b2deb0cfef7167c05f0a641eae2f4cdc848ee
Reviewed-on: https://chromium-review.googlesource.com/369086
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There were checks against global variables trying to determine
failing cases of elog_find_flash(). Instead move the checks
into elog_find_flash() and return value indicating failure.
A minimum 4KiB check was added to ensure the eventlog is at
least that size which makes the heuristic checks cleaner.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16101
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I4d9d13148555e05d4f217a10f995831a0e437fc3
Reviewed-on: https://chromium-review.googlesource.com/369085
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There were 3 variables indicating the state of the event log
region. However, there's no need to keep track of those
individually. The only thing required is to know is if
elog_scan_flash() failed. There's no other tracking required
beyond that.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16100
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I88ad32091d3c37966a2ac6272f8ad95bcc8c4270
Reviewed-on: https://chromium-review.googlesource.com/369084
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There were multiple paths where writes and erases of the flash
were being done. Instead provide a single place for synchronizing
the non-volatile storage from the mirrored event log. This
synchronization point resides as the very last thing done when
adding an event to the log. The shrinking check happens before
committing the event to non-volatile storage so there's no need
to attempt a shrink in elog_init() because any previous events
committed already honored the full threshold.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16099
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Iaec9480eb3116fdc2f823c25d028a4cfb65a6eaf
Reviewed-on: https://chromium-review.googlesource.com/369083
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds a cmos.layout and a cmos.default to ga-g41m-es2l.
This allows to set things like baud_rate, debug_level, etc.
from cmos.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15493
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I25df7a1f3a0ce486b96cfe05bda628f604b0baec
Reviewed-on: https://chromium-review.googlesource.com/369080
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This allows to set the preallocated memory for the IGD on x4x
using a cmos option.
If no cmos option is found a default value of 64M is used.
TESTED most options on ga-g41m-es2l with 2G dimm in one slot and 2x2G.
352M also works in contrast with gm45 where it is known to cause issues
with certain ram combinations.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15492
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I9051d080be82f6dfab37d353252e29b2ed1fca7f
Reviewed-on: https://chromium-review.googlesource.com/368889
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Intel documtentation, "Intel 4 Series Chipset Family"
mentions the possibility of 1, 4, 8 and 16M of preallocated
memory for the IGD, but does not document this.
This allows to set those undocumented values.
TESTED on ga-g41m-es2l with 2G dimm in one slot and 2x2G.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15491
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I92beb8d78907d4514a5aaf69248dd607dcf227c0
Reviewed-on: https://chromium-review.googlesource.com/368888
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This moves the Kconfig from the Super I/O manufacturer folder
to the chip folder instead.
This makes new chip commits self-contained unit as
edits to the central Kconfig file are no longer required.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15973
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I7aee07919f2ae9204850c669e0ed3cb17d4de8cd
Reviewed-on: https://chromium-review.googlesource.com/368886
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the TODO message from FspUpdVpd.h
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16114
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Change-Id: Icd565c6062ef59b1e4a68310bb6f9ed62fb014af
Reviewed-on: https://chromium-review.googlesource.com/368883
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As no more mainboards are utilizing this SoC support code remove
it. It can be resurrected if ever needed.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16108
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ic3caf6e6c9b62d012679b996abaa525c8bf679a9
Reviewed-on: https://chromium-review.googlesource.com/369070
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The rush_ryu board was a development platform that never made it into
a product. Remove it as it's not available to anyone.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16107
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ia3836ff8cade3009730543177a66736ae197572b
Reviewed-on: https://chromium-review.googlesource.com/368959
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The rush board was a development platform that never made it into
a product. Remove it as it's not available to anyone.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16106
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I0f77bb791491509da7bd9cf25050e01c2f734a2f
Reviewed-on: https://chromium-review.googlesource.com/368958
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of treating offsets relative to after the header make
the offsets relative to the in-memory mirror buffer. This
simplifies the logic in that all offsets are treated the same.
It also allows one to remove a global variable.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16098
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I42491e05755d414562b02b6f9ae47f5c357d2f8a
Reviewed-on: https://chromium-review.googlesource.com/368957
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A region_device can be used to represent the in-memory mirror
of the event log. The region_device infrastructure has builtin
bounds checking so there's no need to duplicate that. In addition,
it allows for removing much of the math juggling for the buffer
size, etc.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16097
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic7fe9466019640b449257c5905ed919ac522bb58
Reviewed-on: https://chromium-review.googlesource.com/368956
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There's only 2 users of checking if the event buffer is cleared
to the EOL value. Each were passing pointers of the in-memory
mirror while also doing calculations for the size to check. Since
the in-memory mirror is one big buffer the only thing required
to know is the offset to start checking from. The check is always
done through the end of the buffer.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16096
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Icd4a7edc74407d6578fc93e9eb533abd3aa17277
Reviewed-on: https://chromium-review.googlesource.com/368955
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of forcing the hardcoded 'devicetree.cb' filename under the
mainboard directory, this allows mainboards to select a filename for
the devicetree file.
This allows mainboard variants that need to use different devicetree
files to live under the same directory.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12529
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I761e676ba5d5f70d1fb86656b528f63db169fcef
Reviewed-on: https://chromium-review.googlesource.com/368289
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The elog_flash_erase() was only called to erase the entire
elog region in flash. Therefore, drop the parameters and
perform the full erase.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16094
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I6590347ae60d407bc0df141e9196eb70532f8585
Reviewed-on: https://chromium-review.googlesource.com/368285
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There was a check against the next event offset against
the shrink size in elog_shrink(). However, all calls
to elog_shrink() were conditionalized on the next
event offset exceeding the full threshold. The shrink
size is set to the minimum of the full threshold and
a percentage of the elog region size. Therefore, it's
impossible for the next event offset to be less than
the shrink size because full threshold is always greater
than or equal to the shrink size.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16093
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie6ff106f1c53c15aa36a82223a235a7ac97fd8c7
Reviewed-on: https://chromium-review.googlesource.com/368284
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For the elog shrink case we log the number of bytes shrunk
from the event log. However, when clearing the log the
size recorded was the entire region size including the header
as well as the event region space. To be more consistent
mark the clearing event with the number of bytes actually
cleared out (excluding the header size).
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16092
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7c33da97bd29a90bfe975b1c6f148f181016f13f
Reviewed-on: https://chromium-review.googlesource.com/368283
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The gsmi_exec() expects the parameter to be a pointer
to the 32-bit register storage of the SMI save state.
The previous code was passing a pointer with the value
obtained from the saved-state -- not a pointer to the
storage of the register value. This bug causes gsmi
to not log events because it's interrogating the
parameter buffer itself as if it were a pointer.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16087
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I37981424f1414edad1456b31cad1b99020d57db6
Reviewed-on: https://chromium-review.googlesource.com/368281
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since RTC is now a Kconfig ensure RTC is selected on the
x86 chipsets which are in Chrome OS devices. This allows
the eventlog to have proper timestamps instead of all
zeros.
BUG=chrome-os-partner:55993
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16086
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I24ae7d9b3bf43a5791d4dc04aae018ce17fda72b
Reviewed-on: https://chromium-review.googlesource.com/368280
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
List of changes done here in this patch
1. Remove CARD definition from EMMC and SD Card Controller in scs.asl
since _RMV method does not get evaluated while setting up removable
attribute in sysfs in kernel.
"cat /sys/block/mmcblk1/removable" this command always returns 0.
This CARD Device includes _ADR which follows SDIO Bus format. But,
SD/EMMC sits on PCI Bus.
Hence this CARD Device specific _ADR code is also not needed.
2. Remove Base Address for ACPI debug output memory buffer in
systemagent.asl as it is not getting used throughout the code.
BUG=none
BRANCH=none
TEST=Build and boot kunimitsu
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16068
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I29effaffdafcc21e26445ec3c54aedecdbc50274
Reviewed-on: https://chromium-review.googlesource.com/368277
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Program PIRQ Routing with correct values, as done by FSP, and also in
'soc/intel/skylake/romstage/pch.c' file. If not done, these values get
overridden by "0" during PxRC -> PIRQ programming in ramstage, in
'soc/intel/skylake/lpc.c' file pch_pirq_init()function.
BUG=none
BRANCH=none
TEST=Build and boot kunimitsu
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16044
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ibeb9a64824a71c253e45d6a1c6088abd737cf046
Reviewed-on: https://chromium-review.googlesource.com/368276
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Here is the list of items of code cleanup
1. Define TCO registers in smbus.h and not in pmc.h (as per EDS).
2. Include smbus.h wherever these TCO register defines were used.
3. Remove duplication of define in gpio_defs.h.
4. Remove unnecessary console.h include from memmap.h as no prints done.
5. Remove unnecessary comment from pch.c.
BUG=none
BRANCH=none
TEST=Built and boot kunimitsu.
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16027
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ibe6d2537ddde3c1c7f8ea5ada1bfaa9be79c0e3b
Reviewed-on: https://chromium-review.googlesource.com/368275
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If the CONFIG_CCACHE variable is NOT set, define the CCACHE variable as
blank on the Chrome EC make command line. This will overrride and
disable the CCACHE variable in the Chrome EC makefile.
BUG=None
BRANCH=None
TEST=None
Change-Id: I9492b3af2d6cb746ec285f0bc00bba019229fa17
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16035
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/368783
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of writing the first word of 6 "post code structs" where only
one exists (leading to 0xDEAD and 5 garbage words), write the correct
set.
BUG=None
BRANCH=None
TEST=None
Change-Id: Ic0aefaf938f146b2461b99182db421a73743931c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1361054, #1361055, #1361056
Reviewed-on: https://review.coreboot.org/16058
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/368781
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This replaces all occurrences of a hardcoded vboot path to the
VBOOT_SOURCE variable, that may be overridden from the command line,
witch fallback to the source from 3rdparty.
BUG=None
BRANCH=None
TEST=None
Change-Id: I093657f526a8711866ad208589cc9a3f505cc825
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15825
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368625
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adding kabylake device ids for chip inits.
Skylake and Kabylak do not differ much, the intention
is to support both SoCs in the same code base.
BUG=None
BRANCH=None
TEST=None
Change-Id: I9f985ae9a0c066f1136eabcdf5ef1c849ef0c83a
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16049
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368716
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable I2C bus 2 for early init so it can be used by vboot for TPM
communication for verifying the memory init code.
BUG=chrome-os-partner:53336
BRANCH=none
TEST=build and boot on reef
Change-Id: I6c8857665dbcf495d1ac4fa40b238cd74baa7097
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16059
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368715
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Generate an object to describe the coreboot table region in ACPI
with the HID "CORE0000" so it can be used by kernel drivers.
To keep track of the "CORE" HID usage add them to an enum and add
a function to generate the HID in AML: Name (_HID, "CORExxxx")
BUG=chromium:589817
BRANCH=none
TEST=build and boot on chell, dump SSDT to verify contents:
Device (CTBL)
{
Name (_HID, "CORE0000") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadOnly,
0x7AB84000, // Address Base
0x00008000, // Address Length
)
})
}
Change-Id: Ifa39e378eb1e7c00f03d8d213f52ff3cb9c17606
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16056
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/368714
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
The -b FSP_LOC argument to cbfstool is only valid for the COREBOOT
CBFS. Don't pass that value for all other CBFS regions.
BUG=None
BRANCH=None
TEST=None
Change-Id: Ibc90f238214bdde4f4d3e0d49b1981413d130f1a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14641
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/368713
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
If EC_GOOGLE_CHROMEEC is enabled, ensure that the EC is in correct mode
before running memory init. This saves additional memory training
required in recovery path because of reboot later in ramstage.
BUG=chrome-os-partner:54245
BRANCH=None
TEST=None
Change-Id: I95b25327e4ec8b3c8784dbd34ff150c8c82864ea
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16034
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368712
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
SD CLK and CLK_FB needs to be pulled down by 20K.
SD CD_N is active LOW, needs to be pulled up by 20K
SD WP pin is not connected for uSD cards, enable writes
by default by pulling low by 20K.
BUG=chrome-os-partner:54866
BRANCH=None
TEST=Test with uSD cards.
Change-Id: I613b56cedc5796f22ba4d9fdd52c09a33acd6fef
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Reviewed-on: https://review.coreboot.org/16057
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368711
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
