This reverts commit b57d172fbb.
Reason for revert: Results into hard hang with serial debug msg as
below:
`[EMERG] Unable to unhide the P2SB device!`
Intel team is working towards to fix this issue.
BUG=b:239806774
TEST=Able to boot the Intel/MTLRVP with this revert.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic6be37c000afdf4f0c6c22497c233aa0bbc49d48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65500
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR config on Meteor Lake
to instruct Pad Configuration Lock.
BUG=b:211573253, b:211950520, b:213596994
TEST=Able to perform GPIO lock programming without error on MTLRVP.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icd123adb02716149fa51c9e4c987c281f9de2f43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This patch updates the GPIO lock configuration recommendation
kconfig string to ensure the SoC user can select the correct
config as applicable for the SoC.
Note: From MTL onwards GPIO lock config can be performed using
PCR write (MMIO write) and the GPIO team has confirmed this.
BUG=b:213596994
TEST=Able to fix below GPIO lock config error msg on MTL with
`SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR` kconfig enabled.
[INFO ] Locking pad configuration using SBI
[INFO ] gpio_pad_config_lock_using_sbi: Locking pad 73
configuration
[ERROR] SBI Failure: Transaction Status = 1
[ERROR] Failed to lock GPIO PAD, response = 1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icab1e4849b8e08ee1c695c924599f1513774178f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch ensures the debug consent value is matching with the
inline comment.
TEST=Able to build the Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icf72eb2aa4064fd78f4f99570a4cf44e41932ec3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66008
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hide these ACPI device so Windows does not warn about missing device
drivers.
Change-Id: Iba6cf7a17eefc9f4f247621f6625151f2fd5f3a7
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Set the default value for MAX_CPUS in the SoC config and drop it from
the mainboards where it is set to those values.
Change-Id: Ib56fdcfe770ef736a2c5e183481d9f9966570e6d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Geralt reference design has both eMMC and SD card interfaces, so we have
to configure both in ramstage.
Implement msdc.c (mass storage device class) to place the eMMC and SD
card drivers.
This implementation is based on chapter 5.9 in MT8188 Functional
Specification.
TEST=boot to kernel using emmc successfully.
BUG=b:236331724
Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com>
Change-Id: I6594c8466a133d3fdb0084716acca8dcf785f94f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65975
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because 0 and 1 are the only possible values,
1. Change input argument "enable" of mainboard_enable_regulator to bool.
2. Change return value of mainboard_regulator_is_enabled() to bool.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iae09c5fedf8f7394bfbb677e5aee37ed061304fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65997
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For MT8188, we need to enable and adjust VMCH and VMC to support SD
cards. Therefore, we add VPA and VSIM1 voltage adjustment APIs.
TEST=measure 3.0V in VMCH and VMC.
BUG=b:236331724
Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: I03938f9ef17a0bdd615bcbbfc7b59fa5acb8fbfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65874
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PMIF, SPI, SPMI and PMIC init code.
These PMIC settings are used by MediaTek internally. We can find these
registers in "MT6365_PMIC_Data_Sheet_V1.4.pdf" and
"MT6315 datasheet v1.3.pdf". The setting values are provided by MeidaTek
designers.
TEST=build pass
BUG=b:233720142
Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: I05a51894b130a59c28d957b64d6401c8bb9cee91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
We will use the same drivers for checking ulposc in MT8188, so we add a
new function pmif_ulposc_check() to common.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I40136eaeb2c08a97cd65bfb8a81f2f24739d4d51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65841
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SPI_RESTRICTED_CMD register is not a PCI configuration register. It
is memory mapped from the SPI bar.
Verified against PPR 55570 rev 3.16, PPR 56569 rev 3.03, and PPR 57243
rev 1.50
TEST=Compile tested only
Change-Id: I7c88aaea9ddac200644bb368be3bd4e9be47fd7b
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63305
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Prepare platforms for linking romstage code in the bootblock.
Change-Id: Ic20799b4d6e3f62cd05791a2bd275000a12cc83c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
PSP expects PSP L2 directory address relative to the start of the SPI
ROM. Also PSP does not expect BIOS L2 directory address since it is an
entry in PSP L2 directory. Update the configuration such that PSP
verstage passes the right address to PSP.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that PSP verstage passes the
address as expected by PSP.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8dc3aa4cb401d16a68da446f83eb9e68ee290fea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
On SoCs where PSP use A/B recovery layout, PSP expects PSP L2 directory
address relative to the start of the SPI ROM. Unfortunately there is
nothing in the EFS2 header to help identify such SoCs. Hence add a
config item to statically identify such SoCs.
Also when PSP uses A/B recovery layout, BIOS L2 directory is an entry in
the PSP L2 directory. Hence the address of BIOS L2 directory is not part
of EFS2 header. Thankfully PSP is able to identify the BIOS L2 directory
itself and does not expect PSP verstage to pass the address. Modify PSP
verstage to handle these updates.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that PSP verstage returned the PSP
L2 directory as expected.
Change-Id: I2f856a62055c80b8e2db91c983832611a5f0389c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
PSP supports mapping FCH UART and verstage logs are visible in console.
Hence pre-bootblock cbmem contents do not have to be dumped to console.
BUG=b:238937687
TEST=Build Skyrim BIOS image. Ensure that PSP verstage logs in CBMEM are
not dumped to console again during bootblock.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8336e372b894d8b2f9bbfb21ab15a78527dcc4c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Skyrim uses second SPI pads for ESPI. Switch to it initialize ESPI in
verstage.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that ESPI init is successful in PSP
verstage.
Change-Id: I6e3462e95c50d256b6c159ae1d854dd69a538bb0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Add the CSE, General Status and Miscellaneous registers and
print information from them accordingly. All values were taken
from Intel document number 571993.
Tested on the StarLite Mk III and the correct values are
shown:
[DEBUG] CSE: Working State : 2
[DEBUG] CSE: Manufacturing Mode : NO
[DEBUG] CSE: Operation State : 1
[DEBUG] CSE: FW Init Complete : NO
[DEBUG] CSE: Error Code : 3
[DEBUG] CSE: Operation Mode : 0
[DEBUG] CSE: FPF status : unknown
Please note, the values shown are in an error state.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1a5548132dadbb188a33a7ae30a0a1fa144d130f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When override "max_dram_speed_mts", set the DdrSpeedControl to manual.
(0:Auto, 1:Manual)
BUG=b:229549930
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com>
Change-Id: Iffbbee8082fb1a41e0ed1db3f4ea9ec4709c9ce7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65877
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Guard gpmr_lockdown_cfg with SOC_INTEL_COMMON_BLOCK_GPMR
so it doesn't run on platforms that don't select this.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iab5bbd399c3a654dcb95eaa8fce683a50c7322f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65227
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
In preparation to add a third option, have "Client" platforms select a
dedicated Kconfig option instead of the common "_BASE" option. Rewrite
the help texts to clarify what "Client" and "Server" mean, because the
terms refer to the type of silicon and not to the market segment. Some
uniprocessor (single-socket) servers are actually client platforms and
there are some multi-socket workstations based on a server platform.
Change-Id: I646729d709f60ca2b5e74df18c2b4e52f9b10e6b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Call heci_init to initialise all Heci devices and bring them to d0.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id2865b649331846fc119da7c4be56cc1fed56b8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This allows the mainboard code to change FSP-M parameters depending on
parameters that are only known at run time and not at build time.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e0e196a5d861acd7635c59db44ecf1970b73ce2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Ported back from commit ceaf9d1169 ("soc/intel/alderlake:
Allow possible options for MP Init")
This patch creates choice that lists all possible options to perform
MP Init as below for Intel Meteor Lake platform:
1. MTL_USE_FSP_MP_INIT: Allow coreboot to bring APs from reset and FSP
runs feature programming based and selects MP_SERVICES_PPI_V2 config.
2. MTL_USE_COREBOOT_MP_INIT: Allow coreboot to perform MP Init (both AP
init and feature programming) using native implementation.
Additionally, selects required RELOAD_MICROCODE_PATCH when coreboot
is expected to run MP Init.
Refactor SoC code to allow required FSP UPD override based on
selected MP Init option.
Additionally, added `FIXME` comment to ensure Intel MTL FSP can bring
back SkipMpInit UPD in MTL to let coreboot override this UPD and ensure
independent MP Init flow.
BUG=b:219053812
TEST=Able to build google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic917e4e03e24d73190cfc72c6ed8e59af427bedf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65743
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables coreboot doing Multiprocessor Initialization (MP)
for Meteor Lake CPU using the native coreboot drivers and passes the
MP PPI data structure to let FSP to perform CPU feature programming
(anything that is restricted) as part of FSP-S.
Additionally, modify the kconfig inclusion order alphabetically.
BUG=b:219061518, b:219053812
TEST=Able to bring all APs from reset by coreboot and successfully
able to perform all CPU feature programming using MP PPI services.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic2781ee0b39e42aa579b72d3d4ee6586d5a89a02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65742
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures Intel Meteor Lake can enable the X2APIC feature.
While debugging Intel Meteor Lake (MTL) based platforms it seems like
enabling `DEFAULT_X2APIC` runs into a hang while coreboot tries to
bring the application processors (APs) from reset using X2APIC mode.
[INFO ] LAPIC 0x10 switched to X2APIC mode.
...
[DEBUG] Attempting to start 3 APs
[DEBUG] Waiting for 10ms after sending INIT.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[ERROR] Not all APs checked in: 0/3.
[DEBUG] 0/3 eventually checked in?
[ERROR] MP initialization failure.
[ERROR] MP initialization failure.
Note: The AP bring up flow between XAPIC and X2APIC are the same
except the way to access those LAPIC registers. X2APIC expects to
access all LAPIC registers using MSR (base with 0x800).
The correct flow to enable X2APIC on MTL would be as follows:
1. Let BSP bring all APs in XAPIC mode.
[INFO ] LAPIC 0x10 in XAPIC mode.
...
[DEBUG] Attempting to start 3 APs
[DEBUG] Waiting for 10ms after sending INIT.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[INFO ] LAPIC 0x11 in XAPIC mode.
[INFO ] LAPIC 0x0 in XAPIC mode.
[INFO ] LAPIC 0x80 in XAPIC mode.
2. Call enable_x2apic() function on all CPUs (BSP and APs)
And at the end of #2 above, all cores will now switch to X2APIC
from XAPIC.
[INFO ] Initializing CPU #0
[DEBUG] CPU: vendor Intel device a06a0
[DEBUG] Clearing out pending MCEs
[INFO ] LAPIC 0x10 switched to X2APIC mode.
...
[INFO ] CPU #0 initialized
[INFO ] Initializing CPU #1
[DEBUG] CPU: vendor Intel device a06a0
[DEBUG] Clearing out pending MCEs
[INFO ] LAPIC 0x11 switched to X2APIC mode.
Note: Intel MTL FSP also follow the same steps for x2APIC enablement
while coreboot selects USE_INTEL_FSP_MP_INIT config instead
MP_SERVICES_PPI_V2.
BUG=b:219061518, b:219053812
TEST=Able to perform coreboot doing AP init with
DEFAULT_X2APIC_LATE_WORKAROUND config enabled without running into
any hang issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie9c8fad6c46b15b5b08c9cc4ef53f2a6872bd0ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65741
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit e54a8fd432 (soc/intel/meteorlake:
Add entry for GSPI2 device) added an entry for the GSPI2 device in the
devicetree, but did not add any other entries. Ensure that the rest of
the code is aware of the GSPI2 device to avoid any problems.
Change-Id: Ib59bd289751bd96402c4adc61ffbee3bebe0edb0
Found-by: Coverity CID 1490681
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
The APOB in sabrina is larger than in cezanne/picasso and no longer
fits in the previously allocated 64K space for it. Other symbols are
placed immediately after the APOB region and end up corrupting the APOB
data on sabrina.
Add a Kconfig option to specify the APOB size in DRAM to reserve enough
memory and increase the size for sabrina to 128K
TEST=Timeless builds are identical for mandolin/majolica for PCO/CZN.
Build chausie and verify symbols do not overlap _apob region
BUG=b:224056176
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia5dbacae67ff02fc8a6ec84b9007110ca254daa3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change is to allow AMD MP2 I2C OS driver to access
I2C0/1 devices when MP2 firmware is loaded.
Change-Id: Iaf25eb4dcf949e4b512ec0e86dbe5ccbc91c3d24
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65673
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit makes gsi_bases platform independent. It introduces two new
Kconfigs which set if there are IIO APICs on other devices than the PCH
or not, and where they do start.
Change-Id: I40db4a8fd90572757687f35bbd8eebd7229fc75a
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65531
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is based on the following Intel documents:
* 570805
* 570806
* 572062
* 571264
Change-Id: I199415902d26fa5341ef3212a9169836ea4df74a
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The validation process verifies that hardware components comply with
the standard hardware specifications. For instance, PCI express
implementation must comply with the hardware PCIe specification
requirements: Electrical, Configuration, Link Protocol and Transaction
Protocol. To perform these tests the hardware must be configured in a
particular state: some feature related to power management need to be
turned off, hot plug should be enabled...
This patch sets the appropriate FSP Updateable Product Data flags to
get the hardware in the proper configuration:
- Enable PCIe hotplug on all ports
- Set clock sources to run free
- Set the FSP compliance test mode flag
BUG=b:235863379
TEST=Compilation with and without the flag
Verify code path with instrumentation
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ic07b9276121dfbd273a8f63a1f775ddbd3566884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This config can be used to make coreboot configure the hardware to
meet compliance tests requirements. SoCs which support compliance
testing features should set the
SOC_INTEL_SUPPORTS_COMPLIANCE_TEST_MODE flag.
BUG=b:235863379
TEST=Successful compilation
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Iec760ae89e2b892ef45e6750e823ab5a8609d0fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This moves the die() statement to a common place.
Change-Id: I24c9f00bfee169b4ca57b469c089188ec62ddada
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This allows the compiler to optimize out code called after run_ramstage.
Also remove some die() statements in soc code as run_ramstage already
has a die_with_postcode statement.
Change-Id: Id8b841712661d3257b0dc67b509f97bdc31fcf6f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Since there are many identifiers whose name contain "__unused" in
headers of musl libc, introducing a macro which expands "__unused" to
the source of a util may have disastrous effect during its compiling
under a musl-based platform.
However, it is hard to detect musl at build time as musl is notorious
for having explicitly been refusing to add a macro like "__MUSL__" to
announce its own presence.
Using __always_unused and __maybe_unused for everything may be a good
idea. This is how it works in the Linux kernel, so that would at least
make us match some other standard rather than doing our own thing
(especially since the other compiler.h shorthand macros are also
inspired by Linux).
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
There is an ongoing effort to deprecate VBOOT_VBNV_CMOS, and replace it
with VBOOT_VBNV_FLASH [1]. Since SOC_INTEL_BROADWELL doesn't support
flash writes in early stages (BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES),
drop vboot as well as ChromeOS support for all broadwell boards,
including auron, jecht and wtm2.
[1] https://issuetracker.google.com/issues/235293589
BUG=b:235293589
TEST=./util/abuild/abuild -t GOOGLE_GUADO -a
TEST=./util/abuild/abuild -t GOOGLE_BUDDY -a
Change-Id: I002ab0f5f281c098afba16ada3621f1539c66d6b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This makes it easier to have common code for MP init on AMD systems.
Change-Id: Icb6808edf96a17ec0b3073ba2486b3345a4a66ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This avoids searching the HOB output multiple times when calling
smm_region().
Change-Id: Iad09c3aa3298745ba3ba7012e6bb8cfb8785d525
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
