There are clock settings for usb in mt8195 and mt8188, so we add a new
function which is implemented in pll.c to do this.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I40b358b197541bc5281645879553340059829db3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65750
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This change aligns the Meteor Lake TCSS functions of pad configuration
and Thunderbolt authentication through the sideband access.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Change-Id: I393f6e1c7d322878cbb684cd95bfa2477195b23a
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Use same log level as print_num_status_bits to make sure the
status bits are properly prefix and the newline is added.
Change-Id: Ib33798eec7cba601d0d49646c5fc429de5268417
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65715
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Fixes: 5315e96abf ("arch/x86/postcar: Use a separate stack for C execution")
Resolves:
https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/
thread/TGIWAKZKELJRAEMKJNYRJ55MX2CXYNCV/
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/
thread/2JC3GNJSGXUD6DRVUY7O2O3W6OM3E2MY/
5315e96abf broke platforms using FSP-M to tear down CAR. It was pushing
the value at '_estack' into %esp rather than the address '_estack'.
Change-Id: Ie1fc70bd60fe3a2519ffb71625a35630fa732ff6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65716
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
CPUIDs and Engineering Samples decoding based on DOC #618427.
Keep MICROCODE_BLOB_UNDISCLOSED for PCH-N SKUs as microcode
blobs are still missing.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibb1337e5cbf5b82fdaceb7eb4661d708a32ff0ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65564
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This patch adds the support to enable/disable package c-state demotion
feature from the devicetree based on mainboard requirement.
BUG=b:235005582
TEST=Build and boot to verify that the right value has been passed to
the FSP.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I9e254988bc3d20b9f9e42a605cc0ebd419ab49ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add 0x7d55 as another ID for Meteor Lake graphics controllers.
TEST=Boot with MTL silicon to check coreboot log for DID2
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iea01f6d4f2469fc0eeac73a3f1c4b9af1f39463c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This patch fixes the issue with INTC1056 invalid resource reported by
alderlake-pinctrl Linux driver on ADL-S platform. The driver also
includes GPIO Community 3 in the GPIO list compared to ADL-N which
was missing in GPIO ACPI device.
TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A DDR4 WIFI and check there is
no invalid resource error reported by alderlake-pinctrl
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I23da68c247de86438cc2eef2b5a5a9aa711c1d7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch removes all instances of the `ADL` from Meteor Lake SoC
directory.
TEST=Able to build and boot Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8153b2070467beb582ce1f70be97272ce09ca04c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65667
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates IFD_CHIPSET kconfig value from `ifd2` to `mtl`.
TEST=Able to build and boot Google/Rex image on MTL emulation
platform.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I416f881bcbe3dd7494ead636d6b593366a51b31c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The comment indicates CSE's data partition is placed after BP2. But, it
was place after BP1.So, the patch updates the comment to reflect the
CSE Region layout correctly.
TEST=Build the code for Brya and didn't notice any compilation errors
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ic871e2e395de17157f4f526064a26bfad538707f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
FLASH_DUAL_READ is a common configuration for all MediaTek SoCs, so we
move it to common folder and select it in SoCs' Kconfig.
As suggested in CB:58837, we also rename FLASH_DUAL_READ to
FLASH_DUAL_IO_READ to reduce confusion.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: If267a332519412a7919c5b7817047fabe4a564c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65620
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
gpio_set_pull(), gpio_set_pull_pu_pd() and gpio_set_spec_pull_pupd()
can be reused for mt8192, mt8195 and mt8186, so move it to new file
"gpio_op.c" in common folder.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I81ab9b01ee20fccf3ef29c5902597b5045d3e36a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65641
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
timer_prepare() is the same for MT8195 and MT8186, so move it to
common folder.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I91a6f4ecc665a058cb7a0ba96c15b27d6dc97d13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65602
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add watchdog support for MT8188.
This implementation is based on chapter 3.10.10 in MT8188 Functional
Specification.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iaf56c78d89af53d0272583b463c050e69bbeb07a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65587
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
There are more and more variables which are SoC-specific, so add
soc/wdt.h for each SoC and rename common/wdt.h to
common/wdt_common.h.
wdt_set_req() is almost the same for mt8192, mt8195 and mt8186, so
move it to a common file wdt_req.c.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I7a334b3e7cd4f24a848dd31aca546dc7236d5fb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65636
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Sabrina previously didn't support UART mapping in psp verstage. Now that it has been enabled, add the relevant uart code here.
BUG=b:218709292
TEST=Set serial soft fuse, boot to kernel, check logs
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I591fa69b6e722929839babfff62e9d56c68e1112
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65532
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When compressed ME RW blobs are used for CSE FW update, it has to be
loaded into memory to decompress. So perform CSE FW update in ramstage.
Alder Lake-N based nissa boards use compressed ME RW blobs to save on
SPI flash size. Enable CSE FW update in ramstage.
BRANCH=firmware-brya-14505.B
TEST=Perform CSE FW update on nivviks and verify upgrade/downgrade
works.
Change-Id: Ide9471146d186dca11fb020e5006eeaa01442669
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Some Alder Lake-N boards will use compressed ME RW blobs to obtain
savings on the SPI size (1916KB before compression, ~1132KB after
compression). So add an additional check before calling
cse_fw_sync() from romstage. When compressed blobs are used, the call to
CSE firmware update has to be in post-RAM stages.
BRANCH=firmware-brya-14505.B
Change-Id: I0d9ede52cb493974e4ba6e2e2cf11c9789b3b087
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63760
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch enables X2APIC to avoid hang-ups due to
`Switching from X2APIC to XAPIC mode is not implemented.`
BUG=b:237924211 ([MTL-FSP][v2222.1] Lists of boot issue with MTL FSP)
TEST=Able to enable X2APIC on rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I58649a9a6c9c0ba86856f6aa5fb470e2ef774e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65617
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch sets the Power Limits and Voltage Regulator settings for
three RaptorLake SKUs (45W, 28W and 15W) following the guidance from
document 686872 (June 7th edition).
BUG=b:237809660
TEST=Power Limit and VR serial logs review + debug instrumentation
SKUs successfully booted
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I7e9d4039615e6c33b869c6243efbfeb2259ac219
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65582
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
In reality the expression should not overflow as the value
fits in 32 bits.
Change-Id: I50d83dce25a4d464e1c979502c290d8ecd733018
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
mch_id is set to zero and then unnecessarily tested.
TEST=build and boot image on ADL RVP board
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I4f48742b04edd50fbc0db342b563534e709d6fdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Platform with public FSP hooked-up have an additional parameter
to control CNVi WiFi with CnviWifiCore UPD.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I19efb645fbe1530a571c92d0573c1c60ff6605a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update 3rdparty/fsp submodule to include AlderLake FSP.
Hook up the Kconfig settings to point to Fsp.fd and headers for
ADL-S and ADL-P platforms which the FSP has been published for.
The FSP binaries are compliant with the specification revision 2.3
so update these settings accordingly.
Although FSP header is v2.3 compliant, the features set of the FSP
v2.3 is not being met.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I577931da7952b681534bb78b7b2c7683cd99febd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65519
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This change adds new Rembrandt SoC support by defining it as base SoC
of sabrina as sabrina is derived from Rembrandt SoC.
All the needed changes for Rembrandt SoC will be applied under
SOC_AMD_REMBRANDT config.
Change-Id: I1c9392918cc2c6b511d467f99aceefc725750ce6
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add new folder and basic drivers for Mediatek SoC 'MT8188'.
Difference of modules including in this patch between MT8188 and
existing SoCs:
Timer:
Similar to MT8195 and MT8186, MT8188 uses v2 timer.
EMI/PLL/SPI:
Different from existing SoCs.
The implementation is based on these files:
MT8188G_Application Processor Technical Brief_v0.4.pdf
MT8188G_Functional Specification v0.4.pdf
MT8188 Application Processor Registers-1.pdf
MT8188 Application Processor Registers-2.pdf
TEST=saw the coreboot uart log to bootblock
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I3320f3d49a9b9ed781ceb812e4341e379db4ac20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65585
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot
romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.
BUG=b:237263080
TEST=Able to build and boot MTL simics. Also, verified the FSP debug
log is using coreboot debug library as below:
Before:
Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000F961B000, size is 0x00150000, handle
is 0xF961B000
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
With this code change:
[SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
[SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
[SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
[SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000
[SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
[SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
[SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I80ba73afed642e6d21c5310e9bf734f6f7170347
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add definitions for the GPIO pins on Meteor Lake SoC,
as well as GPIO IRQ routing information and supporting ACPI ASL.
For now, add the following GPIO communities and GPIO groups:
Comm. 0: GPP_CPU, GPP_V, GPP_C
Comm. 1: GPP_A, GPP_E
Comm. 3: GPP_H, GPP_F, SPI0, VGPIO3
Comm. 4: GPP_S, JTAG
Comm. 5: GPP_B, GPP_D, VGPIO
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I7fe9654f22b074a9af18eb7bcdc21812dee77035
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64169
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For ipq806x this fixes two resources getting declared
with same index. The latter previously overwrote former.
Change-Id: Ifee321d930d5433c824e2e977f1bb455766582f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
In ADL-N, cse_fw_sync is done in ramstage. Compile debug_feature.c in
ramstage to fix build error.
BRANCH=firmware-brya-14505.B
Change-Id: I0118b024fce4781cf6008b1c0b416e409fc52065
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63979
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the CSE FW update flow, update is triggered when there is a mismatch
in CSE versions. CSE RW blob is directly mapped from SPI flash, hashed,
compared and then the CSE RW region is updated. However, in the case of
compressed blobs, we cannot directly map the blobs from SPI. It needs to
be decompressed before the hash is calculated and compared. Add a check
for compressed blobs and figure out whether it needs to be directly
mapped from SPI or loaded into memory allocated for file in CBMEM, with
the provided CBMEM ID.
BRANCH=firmware-brya-14505.B
Change-Id: I3bc7708c95272e98702bc25b2334e6e64a93da8a
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CSE FW sync is currently performed in romstage, when uncompressed ME_RW
blobs are used. When compressed blobs are used, this has to be done in
post-RAM stages. Add Kconfigs to describe when the CSE FW sync will be
performed, in romstage or in ramstage.
BRANCH=firmware-brya-14505.B
Change-Id: Iac37aaa5ede5e1cd2d76a58ce2db9cb5b8f42398
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65366
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
