coreboot

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Author	SHA1	Message	Date
Eric W. Biederman	88d4672564	- Cleaner #defines in pirq_routing.h - Remove duplicate include of c_start.S in arch/i386/lib/Config - Infrastructure to handle cpu startup bugs - irq routing table size check - split up the i786 microcode updates into their own files - Enable cpu ECC checking on the Athlons - More pci_ids - #defines for the location of the LinuxBIOS checksum	2003-04-09 00:01:11 +00:00
Eric W. Biederman	fab9293203	Implement CMOS options for the supermicro p4dc6 ECC enable/disable Serial baud rate Debug verbosity	2002-02-01 23:45:30 +00:00
Eric W. Biederman	2beb0a1bcc	- Updates for the supermicro p4dc6 motherboard - Code to initialize sdram from C on the l440gx - cache as ram code fro the p6 it works except conflict misses occur with addresses that are not cached so writing to ram does not work. Which makes it to brittle to count on. - Initial implementation of a fallback booting scheme where we can have two copies of linuxbios in rom at once. - Movement of 32 bit entry code from entry16.inc to entry32.inc - Update of all config files so they now also include entry32.inc - Fix for start_stop.c & entry16.inc so I can fairly arbitrarily relocate the 16bit entry code in SMP. - A small number of fixes for warnings	2001-11-27 19:29:59 +00:00

Author

SHA1

Message

Date

Eric W. Biederman

88d4672564

- Cleaner #defines in pirq_routing.h

- Remove duplicate include of c_start.S in arch/i386/lib/Config
- Infrastructure to handle cpu startup bugs
- irq routing table size check
- split up the i786 microcode updates into their own files
- Enable cpu ECC checking on the Athlons
- More pci_ids
- #defines for the location of the LinuxBIOS checksum

2003-04-09 00:01:11 +00:00

Eric W. Biederman

fab9293203

Implement CMOS options for the supermicro p4dc6

ECC enable/disable
Serial baud rate
Debug verbosity

2002-02-01 23:45:30 +00:00

Eric W. Biederman

2beb0a1bcc

- Updates for the supermicro p4dc6 motherboard

- Code to initialize sdram from C on the l440gx
- cache as ram code fro the p6 it works except conflict misses occur
  with addresses that are not cached so writing to ram does not work.
  Which makes it to brittle to count on.
- Initial implementation of a fallback booting scheme where we can
  have two copies of linuxbios in rom at once.
- Movement of 32 bit entry code from entry16.inc to entry32.inc
- Update of all config files so they now also include entry32.inc
- Fix for start_stop.c & entry16.inc so I can fairly arbitrarily relocate
  the 16bit entry code in SMP.
- A small number of fixes for warnings

2001-11-27 19:29:59 +00:00

3 commits