From ff962b81f424c840ef171d4287a65ab79b018a28 Mon Sep 17 00:00:00 2001
From: Jimmy Zhang <jimmzhang@nvidia.com>
Date: Tue, 11 Feb 2014 17:21:20 -0800
Subject: [PATCH] tegra124: enable JTAG in Security Mode

Once SECURITY_MODE fuse is burned, JTAG is disabled by default.
To reenable JTAG, besides chip unique id and SecureJtagControl need
to be built into BCT, Jtag enable flag is also needed to be set.

BUG=None
TEST=Burn SECURITY_MODE fuse, build chip specific BCT, coreboot
     comes up and jtag hooks up fine.

Change-Id: Ic6b61be2c09b15541400f9766d486a4fcef192a8
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/186031
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/soc/nvidia/tegra/apbmisc.c       | 29 +++++++++++++++++++++++
 src/soc/nvidia/tegra/apbmisc.h       | 35 ++++++++++++++++++++++++++++
 src/soc/nvidia/tegra124/Makefile.inc |  1 +
 src/soc/nvidia/tegra124/bootblock.c  |  4 ++++
 4 files changed, 69 insertions(+)
 create mode 100644 src/soc/nvidia/tegra/apbmisc.c
 create mode 100644 src/soc/nvidia/tegra/apbmisc.h

diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c
new file mode 100644
index 0000000000..fea10b5dbe
--- /dev/null
+++ b/src/soc/nvidia/tegra/apbmisc.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <soc/addressmap.h>
+
+#include "apbmisc.h"
+
+void enable_jtag(void)
+{
+	struct apbmisc *misc = (struct apbmisc *)TEGRA_APB_MISC_BASE;
+	write32(PP_CONFIG_CTL_JTAG, &misc->pp_config_ctl);
+}
diff --git a/src/soc/nvidia/tegra/apbmisc.h b/src/soc/nvidia/tegra/apbmisc.h
new file mode 100644
index 0000000000..805d0bf18b
--- /dev/null
+++ b/src/soc/nvidia/tegra/apbmisc.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA_APBMISC_H__
+#define __SOC_NVIDIA_TEGRA_APBMISC_H__
+
+#include <stdint.h>
+
+struct apbmisc {
+	u32 reserved0[9];		/* ABP_MISC_PP_ offsets 00-20 */
+	u32 pp_config_ctl;		/* _CONFIG_CTL_0, offset 24 */
+};
+
+#define PP_CONFIG_CTL_TBE		(1 << 7)
+#define PP_CONFIG_CTL_JTAG		(1 << 6)
+
+void enable_jtag(void);
+
+#endif	/* __SOC_NVIDIA_TEGRA_APBMISC_H__ */
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index f2e5dc4eaf..5983b36d8d 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -15,6 +15,7 @@ bootblock-y += ../tegra/gpio.c
 bootblock-y += ../tegra/i2c.c
 bootblock-y += ../tegra/pingroup.c
 bootblock-y += ../tegra/pinmux.c
+bootblock-y += ../tegra/apbmisc.c
 bootblock-y += timer.c
 ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
 bootblock-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c
diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c
index 0e10a2b227..22024af90b 100644
--- a/src/soc/nvidia/tegra124/bootblock.c
+++ b/src/soc/nvidia/tegra124/bootblock.c
@@ -23,6 +23,7 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <soc/clock.h>
+#include <soc/nvidia/tegra/apbmisc.h>
 
 #include "pinmux.h"
 #include "power.h"
@@ -31,6 +32,9 @@ void main(void)
 {
 	void *entry;
 
+	// enable JTAG at the earliest stage
+	enable_jtag();
+
 	clock_early_uart();
 
 	// Serial out, tristate off.