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This gets us back to a compiling k8 target.

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This code has been tested on dbe62, and builds for qemu as well. 

the next step is testing on simnow. 

k8.h: add more prototypes and some required inline functions. 
cpu.h: same
serengeti: expand defines in mainboard.h, though we need a better 
mechanism; continue to fix initram.c, add new support files to Makefile
lib/console.c: include globalvars.h
lib/lar.c: Provide more informative print as the lar is scanned.
k8 north: needed reset_test.c from v2, fixes to raminit.c
arch/x86
Kconfig: new CONFIG variable CBMEMK, meaning coreboot mem k, memory
	used for coreboot. 
init_cpus.c: functions to start up CPUs
stage1_mtrr.c: bring over early mtrr support from v2.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@847 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-08-30 03:35:40 +00:00
commit ff2ddcb313
12 changed files with 450 additions and 3 deletions
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2
mainboard/amd/serengeti/Makefile
View file

@ -33,7 +33,9 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/k8/raminit.c \
$(src)/northbridge/amd/k8/dqs.c \
$(src)/northbridge/amd/k8/reset_test.c \
$(src)/arch/x86/pci_ops_conf1.c \
$(src)/arch/x86/stage1_mtrr.c \
$(src)/southbridge/amd/amd8111/stage1_smbus.c \
$(src)/arch/x86/amd/model_fxx/init_cpus.c \
$(src)/arch/x86/amd/model_fxx/dualcore.c \

1
mainboard/amd/serengeti/initram.c
View file

@ -22,6 +22,7 @@
#define _MAINOBJECT
#include <mainboard.h>
#include <config.h>
#include <types.h>
#include <lib.h>
#include <console.h>

5
mainboard/amd/serengeti/mainboard.h
View file

@ -33,7 +33,6 @@
#define SB_HT_CHAIN_UNITID_OFFSET_ONLY 1
#define ENABLE_APIC_EXT_ID 0
#define LIFT_BSP_APIC_ID 1
#warning clean up confusion on FIDVID. v2 was inconsistent.
/* In v2 there is confusion on the settings of these.
* The serengeti config sets it to zero.
@ -44,3 +43,7 @@
/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores,
* so may don't need to do twice */
#define K8_SET_FIDVID_CORE0_ONLY 1
/* architecture stuff which ought to be set "somewhere" "SOMEHOW" */
/* preferably by asking the CPU, not be a DEFINE! */
#define CPU_ADDR_BITS 40