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mb/dell: Add Latitude E5420 (Sandy Bridge)

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Mainboard is Krug 14". I do not physically have this system; someone
with physical access to one sent me the output of autoport which I then
modified to produce this port. I was also sent the VBT binary, which was
obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version
A02 of the vendor firmware.

This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.

This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.

[1] https://gitlab.com/nic3-14159/dell-flash-unlock

Change-Id: I0283653156083768e1fd451bcf539b4e028589f4
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Nicholas Chin 2024-03-04 18:05:43 -07:00 • committed by Felix Singer
commit fef29fc56f
7 changed files with 292 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

10
src/mainboard/dell/snb_ivb_latitude/Kconfig
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@ -17,6 +17,11 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select SYSTEM_TYPE_LAPTOP
select USE_NATIVE_RAMINIT
config BOARD_DELL_LATITUDE_E5420
select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select BOARD_ROMSIZE_KB_6144
select SOUTHBRIDGE_INTEL_BD82X6X
config BOARD_DELL_LATITUDE_E5520
select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select BOARD_ROMSIZE_KB_6144
@ -60,6 +65,7 @@ config MAINBOARD_DIR
default "dell/snb_ivb_latitude"
config MAINBOARD_PART_NUMBER
default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420
default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
@ -74,6 +80,7 @@ config USBDEBUG_HCD_INDEX
default 2
config VARIANT_DIR
default "e5420" if BOARD_DELL_LATITUDE_E5420
default "e5520" if BOARD_DELL_LATITUDE_E5520
default "e6420" if BOARD_DELL_LATITUDE_E6420
default "e6520" if BOARD_DELL_LATITUDE_E6520
@ -82,7 +89,8 @@ config VARIANT_DIR
default "e6530" if BOARD_DELL_LATITUDE_E6530
config VGA_BIOS_ID
default "8086,0116" if BOARD_DELL_LATITUDE_E6520
default "8086,0116" if BOARD_DELL_LATITUDE_E6520 \
|| BOARD_DELL_LATITUDE_E5420
default "8086,0166" if BOARD_DELL_LATITUDE_E5530
default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
|| BOARD_DELL_LATITUDE_E5520

3
src/mainboard/dell/snb_ivb_latitude/Kconfig.name
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@ -1,5 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-only
config BOARD_DELL_LATITUDE_E5420
bool "Latitude E5420"
config BOARD_DELL_LATITUDE_E5520
bool "Latitude E5520"

BIN
src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt Normal file
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Binary file not shown.

14
src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c Normal file
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@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <ec/dell/mec5035/mec5035.h>
#include <southbridge/intel/bd82x6x/pch.h>
void bootblock_mainboard_early_init(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
| COMB_LPC_EN | COMA_LPC_EN);
mec5035_early_init();
}

195
src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c Normal file
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@ -0,0 +1,195 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/common/gpio.h>
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio1 = GPIO_MODE_NATIVE,
.gpio2 = GPIO_MODE_GPIO,
.gpio3 = GPIO_MODE_GPIO,
.gpio4 = GPIO_MODE_GPIO,
.gpio5 = GPIO_MODE_NATIVE,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_NATIVE,
.gpio10 = GPIO_MODE_NATIVE,
.gpio11 = GPIO_MODE_NATIVE,
.gpio12 = GPIO_MODE_GPIO,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_GPIO,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_NATIVE,
.gpio17 = GPIO_MODE_GPIO,
.gpio18 = GPIO_MODE_NATIVE,
.gpio19 = GPIO_MODE_GPIO,
.gpio20 = GPIO_MODE_NATIVE,
.gpio21 = GPIO_MODE_GPIO,
.gpio22 = GPIO_MODE_GPIO,
.gpio23 = GPIO_MODE_NATIVE,
.gpio24 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_NATIVE,
.gpio26 = GPIO_MODE_NATIVE,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
.gpio29 = GPIO_MODE_GPIO,
.gpio30 = GPIO_MODE_GPIO,
.gpio31 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio2 = GPIO_DIR_INPUT,
.gpio3 = GPIO_DIR_INPUT,
.gpio4 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_INPUT,
.gpio12 = GPIO_DIR_OUTPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_INPUT,
.gpio17 = GPIO_DIR_INPUT,
.gpio19 = GPIO_DIR_INPUT,
.gpio21 = GPIO_DIR_INPUT,
.gpio22 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_INPUT,
.gpio27 = GPIO_DIR_INPUT,
.gpio28 = GPIO_DIR_INPUT,
.gpio29 = GPIO_DIR_INPUT,
.gpio30 = GPIO_DIR_OUTPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio12 = GPIO_LEVEL_HIGH,
.gpio30 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio0 = GPIO_INVERT,
.gpio8 = GPIO_INVERT,
.gpio14 = GPIO_INVERT,
};
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_NATIVE,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio36 = GPIO_MODE_GPIO,
.gpio37 = GPIO_MODE_GPIO,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
.gpio40 = GPIO_MODE_NATIVE,
.gpio41 = GPIO_MODE_NATIVE,
.gpio42 = GPIO_MODE_NATIVE,
.gpio43 = GPIO_MODE_NATIVE,
.gpio44 = GPIO_MODE_NATIVE,
.gpio45 = GPIO_MODE_NATIVE,
.gpio46 = GPIO_MODE_GPIO,
.gpio47 = GPIO_MODE_NATIVE,
.gpio48 = GPIO_MODE_GPIO,
.gpio49 = GPIO_MODE_NATIVE,
.gpio50 = GPIO_MODE_GPIO,
.gpio51 = GPIO_MODE_GPIO,
.gpio52 = GPIO_MODE_GPIO,
.gpio53 = GPIO_MODE_GPIO,
.gpio54 = GPIO_MODE_GPIO,
.gpio55 = GPIO_MODE_GPIO,
.gpio56 = GPIO_MODE_GPIO,
.gpio57 = GPIO_MODE_GPIO,
.gpio58 = GPIO_MODE_NATIVE,
.gpio59 = GPIO_MODE_NATIVE,
.gpio60 = GPIO_MODE_GPIO,
.gpio61 = GPIO_MODE_NATIVE,
.gpio62 = GPIO_MODE_NATIVE,
.gpio63 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio33 = GPIO_DIR_INPUT,
.gpio34 = GPIO_DIR_OUTPUT,
.gpio35 = GPIO_DIR_INPUT,
.gpio36 = GPIO_DIR_INPUT,
.gpio37 = GPIO_DIR_OUTPUT,
.gpio38 = GPIO_DIR_INPUT,
.gpio39 = GPIO_DIR_INPUT,
.gpio46 = GPIO_DIR_OUTPUT,
.gpio48 = GPIO_DIR_INPUT,
.gpio50 = GPIO_DIR_OUTPUT,
.gpio51 = GPIO_DIR_OUTPUT,
.gpio52 = GPIO_DIR_INPUT,
.gpio53 = GPIO_DIR_INPUT,
.gpio54 = GPIO_DIR_INPUT,
.gpio55 = GPIO_DIR_OUTPUT,
.gpio56 = GPIO_DIR_INPUT,
.gpio57 = GPIO_DIR_INPUT,
.gpio60 = GPIO_DIR_OUTPUT,
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio34 = GPIO_LEVEL_LOW,
.gpio37 = GPIO_LEVEL_LOW,
.gpio46 = GPIO_LEVEL_HIGH,
.gpio50 = GPIO_LEVEL_HIGH,
.gpio51 = GPIO_LEVEL_LOW,
.gpio55 = GPIO_LEVEL_LOW,
.gpio60 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
};
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio64 = GPIO_MODE_NATIVE,
.gpio65 = GPIO_MODE_NATIVE,
.gpio66 = GPIO_MODE_NATIVE,
.gpio67 = GPIO_MODE_NATIVE,
.gpio68 = GPIO_MODE_NATIVE,
.gpio69 = GPIO_MODE_NATIVE,
.gpio70 = GPIO_MODE_NATIVE,
.gpio71 = GPIO_MODE_NATIVE,
.gpio72 = GPIO_MODE_NATIVE,
.gpio73 = GPIO_MODE_NATIVE,
.gpio74 = GPIO_MODE_GPIO,
.gpio75 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio74 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set3 pch_gpio_set3_level = {
};
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
.reset = &pch_gpio_set1_reset,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
.reset = &pch_gpio_set2_reset,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
.reset = &pch_gpio_set3_reset,
},
};

32
src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c Normal file
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@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x111d76e7, /* Codec Vendor / Device ID: IDT */
0x1028049b, /* Subsystem ID */
11, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(0, 0x1028049b),
AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
AZALIA_PIN_CFG(0, 0x20, 0xd5a30130),
0x80862805, /* Codec Vendor / Device ID: Intel */
0x80860101, /* Subsystem ID */
4, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(3, 0x80860101),
AZALIA_PIN_CFG(3, 0x05, 0x18560010),
AZALIA_PIN_CFG(3, 0x06, 0x18560020),
AZALIA_PIN_CFG(3, 0x07, 0x18560030),
};
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;

39
src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb Normal file
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@ -0,0 +1,39 @@
## SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x1028 0x049b inherit
device ref igd on
register "gpu_cpu_backlight" = "0x00000c31"
register "gpu_pch_backlight" = "0x13121312"
end
chip southbridge/intel/bd82x6x
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
register "usb_port_config" = "{
{ 1, 1, 0 },
{ 1, 1, 0 },
{ 1, 1, 1 },
{ 1, 1, 1 },
{ 1, 1, 2 },
{ 1, 1, 2 },
{ 1, 1, 3 },
{ 1, 1, 3 },
{ 1, 1, 5 },
{ 1, 1, 5 },
{ 1, 1, 7 },
{ 1, 1, 6 },
{ 1, 1, 6 },
{ 1, 1, 7 },
}"
device ref gbe off end
device ref pcie_rp4 off end
device ref pcie_rp7 on end # Broadcom BCM5761 Gigabit Ethernet
device ref sata1 on
register "sata_port_map" = "0x3b"
end
end
end
end