From fea1b2abbe43c50ffd80877eb66b7759b1c57e3d Mon Sep 17 00:00:00 2001 From: Zheng Li Date: Sat, 25 Oct 2025 18:28:54 +0800 Subject: [PATCH] mb/google/nissa/var/pujjocento: Adjust touch panel timing for stability Reduce reset delay from 20ms to 0ms to shorten total tp_rst time from 350ms to 330ms. Validation on Prade shows the controller initializes reliably within the reduced timing. It will be able to complete the following steps before vccs on. 1. TP Reset 2. Get HID Description 3. HID Reset/HID Power On 4. Get Report Descriptor/Get Feature Report Verification results are in b/455053468 comment#3 BUG=b:455053468 BRANCH=none TEST=Build and boot to pujjocento. Verify touchpanel sequence Change-Id: I4efa4e927e78d3200b357f5f5b41c3d2aef12f8b Signed-off-by: Zheng Li Reviewed-on: https://review.coreboot.org/c/coreboot/+/89748 Reviewed-by: Kapil Porwal Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/mainboard/google/brya/variants/pujjocento/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb index 8b7382c8a0..469a880cd6 100644 --- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb @@ -547,7 +547,7 @@ chip soc/intel/alderlake register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)" register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "20" + register "generic.reset_delay_ms" = "0" register "generic.reset_off_delay_ms" = "2" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" register "generic.stop_off_delay_ms" = "2"