UPSTREAM: soc/broadwell: Allow disabling of PCIe ASPM options

The ASPM options (L1 substates, CLKREQ support, Common Clock and ASPM)
are hardcoded for broadwell chips, but some boards may not support
these ASPM options even if the SoC does support it (non-wired CLKREQ
pin for example).
This is required to disable L1 substates on the Purism/Librem 13 which
seems to have issues with NVMe drives falling into L1.2 state and not
being able to exit that state.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ifde46a1db3702a6e1ad49cf3cb03a61d6ffe82d4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b191c9f0ab
Original-Change-Id: I2c7173af1d482cccdc784e3fa44ecbb5d38ddc34
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19899
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531203
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>

src/soc/intel/broadwell/Kconfig

@@ -27,10 +27,6 @@ config CPU_SPECIFIC_OPTIONS
 	select RELOCATABLE_RAMSTAGE
 	select REG_SCRIPT
 	select PARALLEL_MP
-	select PCIEXP_ASPM
-	select PCIEXP_COMMON_CLOCK
-	select PCIEXP_CLK_PM
-	select PCIEXP_L1_SUB_STATE
 	select RTC
 	select SMM_TSEG
 	select SMP
@@ -46,6 +42,22 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_SPI_CONSOLE_SUPPORT
 	select CPU_INTEL_COMMON
 
+config PCIEXP_ASPM
+	bool
+	default y
+
+config PCIEXP_COMMON_CLOCK
+	bool
+	default y
+
+config PCIEXP_CLK_PM
+	bool
+	default y
+
+config PCIEXP_L1_SUB_STATE
+	bool
+	default y
+
 config VBOOT
 	select VBOOT_STARTS_IN_ROMSTAGE