testing
This commit is contained in:
Ronald G. Minnich
parent
6af49778ff
commit
fdea4f1229
8 changed files with 527 additions and 0 deletions
146
src/arch/alpha/config/crt0.base
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146
src/arch/alpha/config/crt0.base
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/*
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* $ $
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*
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*/
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.set noat
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.set noreorder
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.text
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#include <arch/cpu.h>
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#if USE_CPU_EV4
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#include <cpu/ev4/start.inc>
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#elif USE_CPU_EV5
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#include <cpu/ev5/start.inc>
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#elif USE_CPU_EV6
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#include <cpu/ev6/start.inc>
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#else
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#error Uknown alpha cpu type
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#endif
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/* __fatal_error_pal Called with:
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* a0 - Exception handler address that caught the exception
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* a1 - Address where the exception occured.
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* a2 - Potentially valid return address from the code
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* that took the exception.
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*/
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FETCH_BLOCK_ALIGN
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__fatal_error_non_pal:
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/* Resetup the global pointers */
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ldgp gp, 0(pv)
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lda sp, _estack
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/* Display an error message */
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jsr ra, fatal_error
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br zero, .-4
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/* On entry to kernel_mode_start.
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* a0 - Signature (0xDEC?????) likely (0xDECB001)
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* a1 - Memory size in bytes
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* a2 - Cpu speed in picoseconds
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*
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* These parameters should be available on the 164 & the 264.
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*/
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FETCH_BLOCK_ALIGN
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kernel_mode_start:
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/* Setup the global pointers */
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ldgp gp, 0(pv)
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lda sp, _estack
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/* Zero the Bss */
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lda t1, _bss
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lda t2, _ebss
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subq t2, t1, t2
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br Zstart
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Zero: subq t2, 8, t2
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stq zero, 0(t1)
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Zstart: bne t2, Zero
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/* Test for the srom valid signature */
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lda t1, 0xDEC(zero)
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srl a0, 20, t2
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cmpeq t1, t2, t3
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beq t3, 1f
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/* Compute the number of cpu clocks per bit out to the srom
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* debug port.
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*/
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bis a2, a2, t11
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ldq t10, picosecs_per_srom_clock
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jsr t9, __divq
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lda t11, srom_wait_reps
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stq t12, 0(t11)
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1:
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/* Jump to main */
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jsr ra, hardwaremain
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br zero, .-4 /* spin in place */
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.p2align 3
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picosecs_per_srom_clock:
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.quad 104166666 /* Pico seconds per tick of a 9600Hz clock */
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srom_wait_reps:
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.quad 0 /* 48562 on a 466Mhz EV6 */
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/* Wait bit time is private and should not be called from C */
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FETCH_BLOCK_ALIGN
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wait_bit_time:
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#if USE_CPU_EV6
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lda t8, 0x1(zero)
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sll t8, 32, t8 /* t8 = 1.0000.0000 */
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hw_mtpr t8, EV6__CC_CTL /* clear cycle count */
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bis zero,zero,zero /* nop */
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bis zero,zero,zero /* nop */
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bis zero,zero,zero /* nop */
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hw_mtpr zero, (EV6__EXC_ADDR+32) /* dummy IPR write - sets SCBD bit 5 (to stall untill cc_ctl gets written) */
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#else
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hw_mtpr t8, ccCtl /* clear cycle count */
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STALL /* wait 3 cycles to avoid palcode */
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STALL /* violation */
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STALL
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STALL
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#endif
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wait: /* REPEAT */
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rpcc t8 /* : read the cycle count */
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zapnot t8, 0x0f, t8 /* : clear the high longword */
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cmplt t12, t8, t8 /* : */
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beq t8, wait /* UNTIL we have waited time specified */
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ret zero, (t10)
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GLOBL(srom_tx_byte)
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/* Initialze routine variables */
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ldgp gp, 0(pv)
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ldq t12, (srom_wait_reps - srom_tx_byte)(pv)
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lda t11, 16(zero) /* 1 high + 1 start + 8 data + */
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/* 6 stop (5 extra for delay). */
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lda a0, 0x3F00(a0) /* add stop bits at the end and */
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s4addq a0, 1, a0 /* then add start and high bit */
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#if USE_CPU_EV6
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FETCH_BLOCK_ALIGN /* align with nop instructions */
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data_bit: /* REPEAT */
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hw_mfpr t9, EV6__I_CTL /* get current I_CTL value */
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lda t8, 0x1(zero) /* t8 - mask for sl_xmit bit */
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sll t8, EV6__I_CTL__SL_XMIT__S, t8 /* move to the correct position */
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bic t9, t8, t9 /* clear sl_xmit bit in old I_CTL value */
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blbc a0, send_bit /* check the new sl_xmit bit */
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bis t9, t8, t9 /* set sl_xmit bit in old I_CTL value */
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send_bit: /* continue */
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hw_mtpr t9, EV6__I_CTL /* EV6 Send the data bit */
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#else
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sll a0, (SLXMIT_V_TMT), a0 /* Put bits into position */
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data_bit: /* REPEAT */
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hw_mtpr a0, slXmit /* EV5 Send the first bit */
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#endif
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srl a0, 1, a0 /* Shift right, to the next bit. */
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subq t11, 1, t11 /* Decrement the bit count. */
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bsr t10, wait_bit_time /* Wait for a bit time */
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bne t11, data_bit /* UNTIL all data sent */
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ret zero, (ra)
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100
src/arch/alpha/config/ldscript.base
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100
src/arch/alpha/config/ldscript.base
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@ -0,0 +1,100 @@
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OUTPUT_FORMAT("elf64-alpha")
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ENTRY(__start_offset)
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PHDRS { kernel PT_LOAD AT(0x310000); }
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__start_offset = start + 0x310000;
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SECTIONS
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{
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. = _ROMBASE;
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/*
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* First we place the code and read only data (typically const declared).
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* This get placed in rom.
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*/
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.text : {
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_text = .;
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*(.text)
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_etext = .;
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} : kernel
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.rodata : {
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_rodata = .;
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*(.rodata);
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_erodata = .;
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} : kernel
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. = _RAMBASE;
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/* Global data */
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.data : {
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_data = .;
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*(.data.cacheline_aligned)
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*(.data) CONSTRUCTORS
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*(.got)
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*(.sdata)
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_edata = .;
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}
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_ldata = LOADADDR(.data);
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_eldata = LOADADDR(.data) + SIZEOF(.data);
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/* Important align _bss so bss may be zeroed with quadword access */
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. = ALIGN(8);
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.bss : {
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_bss = .;
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*(.sbss)
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*(.scommon)
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*(.bss)
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*(COMMON)
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/* Important align _ebss so bss may be zeroed with quadword access */
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. = ALIGN(8);
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_ebss = .;
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}
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_end = .;
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/* Align the heap to a quadword boundary */
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. = ALIGN(8);
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.heap : {
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_heap = .;
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/* Reserve a meg for the heap */
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. = . + 1024*1024;
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. = ALIGN(8);
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_eheap = .;
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}
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. = ALIGN(8);
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.stack : {
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_stack = .;
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/* Allocate an 8k stack that grows backwards into the heap */
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. = . + 8192;
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. = ALIGN(8);
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_estack = .;
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}
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/DISCARD/ : {
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/* Comment sections */
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*(.mdebug)
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*(.note)
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*(.comment)
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/* DWARF 1 */
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*(.debug)
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*(.line)
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/* GNU DWARF 1 extensions */
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*(.debug_srcinfo)
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*(.debug_sfnames)
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/* DWARF 1.1 and DWARF 2 */
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*(.debug_aranges)
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*(.debug_pubnames)
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/* DWARF 2 */
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*(.debug_info)
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*(.debug_abbrev)
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*(.debug_line)
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*(.debug_frame)
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*(.debug_str)
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*(.debug_loc)
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*(.debug_macinfo)
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/* SGI/MIPS DWARF 2 extensions */
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*(.debug_weaknames)
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*(.debug_funcnames)
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*(.debug_typenames)
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*(.debug_varnames)
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/* Kernel module cleanup sections */
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*(.text.exit)
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*(.data.exit)
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}
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}
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35
src/arch/alpha/config/make.base
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35
src/arch/alpha/config/make.base
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biosbase 0
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rambase 0x10000
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makedefine LINK = ld -T ldscript.ld -o $@ crt0.o linuxbios.a
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makedefine CPPFLAGS= -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include $(CPUFLAGS)
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makedefine CFLAGS= $(CPU_OPT) $(CPPFLAGS) -O2 -nostdinc -nostdlib -fno-builtin -Wall
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makedefine CC=cc
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makerule all : linuxbios.rom ;
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makerule linuxbios.rom: linuxbios.strip makerom ; ./makerom -l0x310000 -i7 -v linuxbios.strip -o linuxbios.rom
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makerule linuxbios.strip: linuxbios ; objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip
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makerule linuxbios: linuxbios.a ; @rm -f biosobject
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addaction linuxbios $(LINK)
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addaction linuxbios nm -n linuxbios > linuxbios.map
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makerule linuxbios.a : $(OBJECTS) ; rm -f linuxbios.a
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addaction linuxbios.a ar cr linuxbios.a $(OBJECTS)
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makerule crt0.s: crt0.S ; $(CC) $(CPPFLAGS) -I$(TOP)/src -E $< > crt0.s
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makerule crt0.o : crt0.s; $(CC) $(CPU_OPT) -c crt0.s
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#makerule makerom: $(TOP)/util/makerom/makerom.c $(TOP)/util/makerom/compress.c ; $(CC) -o makerom $(TOP)/util/makerom/makerom.c $(TOP)/util/makerom/compress.c
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makerule clean : ; rm -f linuxbios.* *.o mkrom xa? *~
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addaction clean rm -f linuxbios crt0.s
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addaction clean rm -f a.out *.s *.l
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addaction clean rm -f TAGS tags
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addaction clean rm -f docipl
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# do standard config files that the user need not specify
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# for now, this is just 'lib', but it may be more later.
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dir /src/arch/alpha
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dir /src/lib
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dir /src/boot
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dir /src/rom
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dir /util/makerom
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18
src/arch/alpha/include/arch/asm.h
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18
src/arch/alpha/include/arch/asm.h
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#ifndef ALPHA_ARCH_ASM_H
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#define ALPHA_ARCH_ASM_H
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/* assembly language utility macros */
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/* Load immediate signed constants */
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#define LOAD_CONSTANT16(reg, constant) \
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lda reg, (constant)(zero)
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#define LOAD_CONSTANT32(reg, constant) \
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ldah reg, ((constant + 0x8000) >> 16)(zero) ; \
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lda reg, (constant & 0xffff)(reg)
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/* Declare a global symbol */
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#define GLOBL(label) .globl label ; label:
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#endif /* ALPHA_ARCH_ASM_H */
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84
src/arch/alpha/include/arch/compiler.h
Normal file
84
src/arch/alpha/include/arch/compiler.h
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#ifndef ALPHA_COMPILER_H
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#define ALPHA_COMPILER_H
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/*
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* Herein are macros we use when describing various patterns we want to GCC.
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* In all cases we can get better schedules out of the compiler if we hide
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* as little as possible inside inline assembly. However, we want to be
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* able to know what we'll get out before giving up inline assembly. Thus
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* these tests and macros.
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*/
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#if 0
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#define __kernel_insbl(val, shift) \
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(((unsigned long)(val) & 0xfful) << ((shift) * 8))
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#define __kernel_inswl(val, shift) \
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(((unsigned long)(val) & 0xfffful) << ((shift) * 8))
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#define __kernel_insql(val, shift) \
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((unsigned long)(val) << ((shift) * 8))
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#else
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#define __kernel_insbl(val, shift) \
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({ unsigned long __kir; \
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__asm__("insbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
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__kir; })
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#define __kernel_inswl(val, shift) \
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({ unsigned long __kir; \
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__asm__("inswl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
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__kir; })
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#define __kernel_insql(val, shift) \
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({ unsigned long __kir; \
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__asm__("insql %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
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__kir; })
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#endif
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#if 0 && (__GNUC__ > 2 || __GNUC_MINOR__ >= 92)
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#define __kernel_extbl(val, shift) (((val) >> (((shift) & 7) * 8)) & 0xfful)
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#define __kernel_extwl(val, shift) (((val) >> (((shift) & 7) * 8)) & 0xfffful)
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#else
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#define __kernel_extbl(val, shift) \
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({ unsigned long __kir; \
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__asm__("extbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
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__kir; })
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#define __kernel_extwl(val, shift) \
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({ unsigned long __kir; \
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__asm__("extwl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
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__kir; })
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#endif
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/*
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* Beginning with EGCS 1.1, GCC defines __alpha_bwx__ when the BWX
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* extension is enabled. Previous versions did not define anything
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* we could test during compilation -- too bad, so sad.
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*/
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#if defined(__alpha_bwx__)
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#define __kernel_ldbu(mem) (mem)
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#define __kernel_ldwu(mem) (mem)
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#define __kernel_stb(val,mem) ((mem) = (val))
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#define __kernel_stw(val,mem) ((mem) = (val))
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#else
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#define __kernel_ldbu(mem) \
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({ unsigned char __kir; \
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__asm__("ldbu %0,%1" : "=r"(__kir) : "m"(mem)); \
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__kir; })
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#define __kernel_ldwu(mem) \
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({ unsigned short __kir; \
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__asm__("ldwu %0,%1" : "=r"(__kir) : "m"(mem)); \
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__kir; })
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#define __kernel_stb(val,mem) \
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__asm__("stb %1,%0" : "=m"(mem) : "r"(val))
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#define __kernel_stw(val,mem) \
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__asm__("stw %1,%0" : "=m"(mem) : "r"(val))
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#endif
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/* Somewhere in the middle of the GCC 2.96 development cycle, we implemented
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a mechanism by which the user can annotate likely branch directions and
|
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expect the blocks to be reordered appropriately. Define __builtin_expect
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to nothing for earlier compilers. */
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#if __GNUC__ == 2 && __GNUC_MINOR__ < 96
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#define __builtin_expect(x, expected_value) (x)
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#endif
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#endif /* ALPHA_COMPILER_H */
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64
src/arch/alpha/include/arch/cpu.h
Normal file
64
src/arch/alpha/include/arch/cpu.h
Normal file
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#ifndef ALPHA_CPU_H
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#define ALPHA_CPU_H
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/* Alpha Logical Register Definitions
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* =========================================================
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*/
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/* Return value */
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#define v0 $0
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/* temporaries */
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#define t0 $1
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#define t1 $2
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#define t2 $3
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#define t3 $4
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#define t4 $5
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#define t5 $6
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#define t6 $7
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#define t7 $8
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#define t8 $22
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#define t9 $23
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#define t10 $24
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#define t11 $25
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#define t12 $27
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/* Saved registers */
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#define s0 $9
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#define s1 $10
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#define s2 $11
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#define s3 $12
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#define s4 $13
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#define s5 $14
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#define s6 $15
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/* Frame pointer */
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#define fp $15
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/* Argument registers */
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#define a0 $16
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#define a1 $17
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#define a2 $18
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#define a3 $19
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#define a4 $20
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#define a5 $21
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/* return address */
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#define ra $26
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/* Procedure value */
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#define pv $27
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/* Assember temporary */
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#define at $28
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/* Global pointer */
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#define gp $29
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/* Stack Pointer */
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#define sp $30
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/* zero */
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#define zero $31
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#if USE_CPU_EV4
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#include <cpu/ev4/dc21064.h>
|
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#elif USE_CPU_EV5
|
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#include <cpu/ev5/dc21164.h>
|
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#elif USE_CPU_EV6
|
||||
#include <cpu/ev6/dc21264.h>
|
||||
#else
|
||||
#error Uknown alpha cpu type
|
||||
#endif
|
||||
|
||||
#endif /* ALPHA_CPU_H */
|
||||
29
src/arch/alpha/include/arch/io.h
Normal file
29
src/arch/alpha/include/arch/io.h
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
#ifndef ALPHA_IO_H
|
||||
#define ALPHA_IO_H
|
||||
|
||||
#include <arch/compiler.h>
|
||||
|
||||
#define mb() \
|
||||
__asm__ __volatile__("mb": : :"memory")
|
||||
|
||||
#define rmb() \
|
||||
__asm__ __volatile__("mb": : :"memory")
|
||||
|
||||
#define wmb() \
|
||||
__asm__ __volatile__("wmb": : :"memory")
|
||||
|
||||
/*
|
||||
* Virtual -> physical identity mapping starts at this offset
|
||||
*/
|
||||
#ifdef USE_48_BIT_KSEG
|
||||
#define IDENT_ADDR 0xffff800000000000
|
||||
#else
|
||||
#define IDENT_ADDR 0xfffffc0000000000
|
||||
#endif
|
||||
|
||||
#if defined(USE_CORE_TSUNAMI)
|
||||
#include <northbridge/alpha/tsunami/core_tsunami.h>
|
||||
#else
|
||||
#error "What system is this?"
|
||||
#endif
|
||||
#endif /* ALPHA_IO_H */
|
||||
51
src/arch/alpha/include/arch/pal.h
Normal file
51
src/arch/alpha/include/arch/pal.h
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
#ifndef __ALPHA_PAL_H
|
||||
#define __ALPHA_PAL_H
|
||||
|
||||
/*
|
||||
* Common PAL-code
|
||||
*/
|
||||
#define PAL_halt 0
|
||||
#define PAL_cflush 1
|
||||
#define PAL_draina 2
|
||||
#define PAL_bpt 128
|
||||
#define PAL_bugchk 129
|
||||
#define PAL_chmk 131
|
||||
#define PAL_callsys 131
|
||||
#define PAL_imb 134
|
||||
#define PAL_rduniq 158
|
||||
#define PAL_wruniq 159
|
||||
#define PAL_gentrap 170
|
||||
#define PAL_nphalt 190
|
||||
|
||||
/*
|
||||
* VMS specific PAL-code
|
||||
*/
|
||||
#define PAL_swppal 10
|
||||
#define PAL_mfpr_vptb 41
|
||||
|
||||
/*
|
||||
* OSF specific PAL-code
|
||||
*/
|
||||
#define PAL_cserve 9
|
||||
#define PAL_wripir 13
|
||||
#define PAL_rdmces 16
|
||||
#define PAL_wrmces 17
|
||||
#define PAL_wrfen 43
|
||||
#define PAL_wrvptptr 45
|
||||
#define PAL_jtopal 46
|
||||
#define PAL_swpctx 48
|
||||
#define PAL_wrval 49
|
||||
#define PAL_rdval 50
|
||||
#define PAL_tbi 51
|
||||
#define PAL_wrent 52
|
||||
#define PAL_swpipl 53
|
||||
#define PAL_rdps 54
|
||||
#define PAL_wrkgp 55
|
||||
#define PAL_wrusp 56
|
||||
#define PAL_wrperfmon 57
|
||||
#define PAL_rdusp 58
|
||||
#define PAL_whami 60
|
||||
#define PAL_rtsys 61
|
||||
#define PAL_rti 63
|
||||
|
||||
#endif /* __ALPHA_PAL_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue