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cpu/intel/smm/gen1: Optimize cpu_has_alternative_smrr

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For most targets it's known if the CPU supports alternative SMRR
registers or not. Only on model_6fx runtime detection is necessary.

On all platforms this allows the compiler to optimize the code and
thus shrink the code size if alternative SMRR aren't supported.

TEST=On Lenovo X220 the ramstage is 308 bytes smaller.

Change-Id: I3a965d142f79ad587b8cedc9b4646b05e2a45f8b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91014
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Patrick Rudolph 2026-01-30 15:19:59 +01:00 • committed by Matt DeVillier
commit fd2cdf206d
3 changed files with 9 additions and 14 deletions
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2
src/include/cpu/intel/smm_reloc.h
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@ -51,8 +51,6 @@ void smm_initialize(void);
void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size);
void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase);
bool cpu_has_alternative_smrr(void);
#define MSR_PRMRR_PHYS_BASE 0x1f4
#define MSR_PRMRR_PHYS_MASK 0x1f5
#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4