erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Enable caching for Via C7 CPUs, and also improve readability. Tested on hardware

Browse source 
and seems to be working.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1164 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Corey Osgood 2009-04-14 15:41:33 +00:00
commit fcf66e3605
3 changed files with 23 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

2
mainboard/jetway/Kconfig
View file

@ -28,7 +28,7 @@ config BOARD_JETWAY_J7F2
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237
select SUPERIO_FINTEK_F71805F
select PIRQ_TABLE
## select PIRQ_TABLE
help
Jetway J7F2-Series board.
endchoice