erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

vc/google/chromeos: Always use CHROMEOS_RAMOOPS_DYNAMIC

Browse source 
Always allocate RAMOOPS from CBMEM and drop the related
static variable CHROMEOS_RAMOOPS_RAM_START.

Change-Id: Icfcf2991cb78cc6e9becba14cac77a04d8ada56a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50608
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2021-02-10 19:31:26 +02:00
commit fce36e448d
17 changed files with 3 additions and 111 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/soc/intel/alderlake/Kconfig
View file

@ -213,9 +213,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0x7fff
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_MUST_REQUEST_DISPLAY

3
src/soc/intel/apollolake/Kconfig
View file

@ -114,9 +114,6 @@ config MAX_CPUS
int
default 4
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_MUST_REQUEST_DISPLAY

3
src/soc/intel/baytrail/Kconfig
View file

@ -37,9 +37,6 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON
select CPU_HAS_L2_ENABLE_MSR
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE

3
src/soc/intel/braswell/Kconfig
View file

@ -52,9 +52,6 @@ config DCACHE_BSP_STACK_SIZE
The amount of anticipated stack usage in CAR by bootblock and
other stages.
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE

3
src/soc/intel/broadwell/Kconfig
View file

@ -73,9 +73,6 @@ config BROADWELL_VBOOT_IN_BOOTBLOCK
binary is used meaning a jump is made from RW to the RO region
and back to the RW region after the binary is done.
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK

3
src/soc/intel/cannonlake/Kconfig
View file

@ -260,9 +260,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0xc35
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_MUST_REQUEST_DISPLAY

3
src/soc/intel/elkhartlake/Kconfig
View file

@ -171,9 +171,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0xc35
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_MUST_REQUEST_DISPLAY

3
src/soc/intel/icelake/Kconfig
View file

@ -164,9 +164,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0xc35
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_MUST_REQUEST_DISPLAY

3
src/soc/intel/jasperlake/Kconfig
View file

@ -172,9 +172,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0xc35
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_MUST_REQUEST_DISPLAY

3
src/soc/intel/skylake/Kconfig
View file

@ -92,9 +92,6 @@ config CPU_INTEL_NUM_FIT_ENTRIES
int
default 10
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_MUST_REQUEST_DISPLAY

3
src/soc/intel/tigerlake/Kconfig
View file

@ -191,9 +191,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0x7fff
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
# Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection
# in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses.
config TPM_CR50