From fcd716d9a272461da1fdbaf1c048eb5a52c7896b Mon Sep 17 00:00:00 2001 From: Sowmya Aralguppe Date: Wed, 14 Jan 2026 13:58:56 +0530 Subject: [PATCH] mb/google/ocelot: Limit Power Limit when battery is missing Ensure the board can boot by limiting the power limits if the battery is missing. This addresses the factory use case for Wildcat Lake processors. BUG=b:None TEST= Use cutoff at-shutdown and reboot The device should boot with reduced power limits value and the log is as shown below [INFO ] Battery not connected, booting with reduced PL values [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (35000, 35000) PL4 (W) (45) Change-Id: Iadb9c4c8450e6a55dd9fc644785742cc7aafd671 Signed-off-by: Sowmya Aralguppe Reviewed-on: https://review.coreboot.org/c/coreboot/+/90755 Reviewed-by: Pranava Y N Reviewed-by: Avi Uday Tested-by: build bot (Jenkins) --- .../variants/baseboard/ocelot/ramstage.c | 53 +++++++++++++++++-- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c b/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c index 43a82d12c3..e68010d3b7 100644 --- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c +++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c @@ -3,6 +3,51 @@ #include #include +/* + * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), + * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) + */ +/* Define a macro for the common power limit values for WCL */ +#define COMMON_WCL_POWER_LIMITS \ + .pl1_min_power = 10000, \ + .pl1_max_power = 15000, \ + .pl2_min_power = 35000, \ + .pl2_max_power = 35000, \ + .pl4_power = 45000 + +const struct cpu_tdp_power_limits power_optimized_limits[] = { + { + .mch_id = PCI_DID_INTEL_WCL_ID_1, + .cpu_tdp = TDP_15W, + .power_limits_index = WCL_CORE, + COMMON_WCL_POWER_LIMITS + }, + { + .mch_id = PCI_DID_INTEL_WCL_ID_2, + .cpu_tdp = TDP_15W, + .power_limits_index = WCL_CORE, + COMMON_WCL_POWER_LIMITS + }, + { + .mch_id = PCI_DID_INTEL_WCL_ID_3, + .cpu_tdp = TDP_15W, + .power_limits_index = WCL_CORE, + COMMON_WCL_POWER_LIMITS + }, + { + .mch_id = PCI_DID_INTEL_WCL_ID_4, + .cpu_tdp = TDP_15W, + .power_limits_index = WCL_CORE, + COMMON_WCL_POWER_LIMITS + }, + { + .mch_id = PCI_DID_INTEL_WCL_ID_5, + .cpu_tdp = TDP_15W, + .power_limits_index = WCL_CORE, + COMMON_WCL_POWER_LIMITS + }, +}; + /* * Placeholder to check if variant has support for barrel jack for powering * on the device. @@ -21,7 +66,9 @@ void baseboard_devtree_update(void) if (variant_is_barrel_charger_present()) return; - /* TODO: Add power limit override code for Wildcat Lake */ - if (!google_chromeec_is_battery_present()) - printk(BIOS_DEBUG, "TODO: Add support for power optimized boot configuration limits\n"); + if (!google_chromeec_is_battery_present()) { + printk(BIOS_INFO, "Battery not connected, booting with reduced PL values\n"); + variant_update_cpu_power_limits(power_optimized_limits, + ARRAY_SIZE(power_optimized_limits)); + } }