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UPSTREAM: soc/intel/skylake: Disable Legacy PME for Root ports

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Legacy PME are enabled by default in FSP UPD region.
When Legacy PME is enabled, then an SCI is generated and should be
handled by OS and BIOS/Coreboot in collboration. OS requires some
ACPI methods (eg _L69) which help to determine the wake source and also
to clear some registers. But this infrastructure is not present as of
now in coreboot and also linux handles PMEs natively.

Hence the SCI was never handled by OS and the status bits were never
cleared i.e., PCI_EXP_STS.

For this reason the level triggered SCI will remain active and the
system will wake up as soon as it enters S3.

To fix this, diabled Legacy PME (PmSci for Root ports).

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17553
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I61317eb45305bdb14be3cc1a54fd9961d6ed593e
Reviewed-on: https://chromium-review.googlesource.com/411573
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Naresh G Solanki 2016-11-16 21:27:38 +05:30 • committed by chrome-bot
commit fc0c6dea3d
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/skylake/chip_fsp20.c
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@ -157,6 +157,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
sizeof(params->PcieRpClkReqNumber));
/* disable Legacy PME */
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
sizeof(params->SerialIoDevMode));