From fbb68982c95b1599ee70e8f8b5c5448c82ad2aa2 Mon Sep 17 00:00:00 2001 From: Appukuttan V K Date: Wed, 20 Aug 2025 22:31:16 +0530 Subject: [PATCH] mainboard/google/ocelot: Update PCIe root port for SD card interface This commit updates the PCIe root port configuration for the SD card interface in the overridetree.cb file for the Ocelot variant. The reference is changed from `pcie_rp5` to `pcie_rp6`. BUG=b:440042829 TEST=Boot the device with the updated firmware and verify that the SD card is enumerated under pcie_rp6 Change-Id: I2b3c0b6e19409fef933aa7dc06f5df035f620738 Signed-off-by: Appukuttan V K Reviewed-on: https://review.coreboot.org/c/coreboot/+/88873 Reviewed-by: Usha P Reviewed-by: Nick Vaccaro Reviewed-by: Pranava Y N Reviewed-by: Krishna P Bhat D Tested-by: build bot (Jenkins) --- src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb index 59273e4bd3..011b03352a 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb @@ -478,10 +478,10 @@ chip soc/intel/pantherlake end end # Gen4 M.2 SSD - device ref pcie_rp5 on + device ref pcie_rp6 on probe SD SD_GENSYS probe SD SD_BAYHUB - register "pcie_rp[PCIE_RP(5)]" = "{ + register "pcie_rp[PCIE_RP(6)]" = "{ .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,