diff --git a/src/mainboard/google/brya/acpi/cnvi_bt_reset.asl b/src/mainboard/google/brya/acpi/cnvi_bt_reset.asl
new file mode 100644
index 0000000000..e2a387aee1
--- /dev/null
+++ b/src/mainboard/google/brya/acpi/cnvi_bt_reset.asl
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <variant/gpio.h>
+
+/* If variants use other GPIO for BT_RESET
+   Define it at variant/gpio.h */
+#ifndef BT_RESET_GPIO
+#define BT_RESET_GPIO	GPP_D4
+#endif
+
+#define CNV_BTEN		GPP_VGPIO_0
+#define CNV_BT_IF_SELECT	GPP_VGPIO_5
+
+External (\_SB.PCI0.CTXS, MethodObj)
+External (\_SB.PCI0.STXS, MethodObj)
+
+Scope (\_SB.PCI0.XHCI.RHUB.HS10)
+{
+	PowerResource (CTTR, 0x00, 0x0000)
+	{
+		Method (_STA, 0, NotSerialized)  // _STA: Status
+		{
+			Return (One)
+		}
+
+		Method (_ON, 0, NotSerialized)  // _ON_: Power On
+		{
+			\_SB.PCI0.STXS(CNV_BTEN);
+			\_SB.PCI0.STXS(CNV_BT_IF_SELECT);
+			\_SB.PCI0.STXS(BT_RESET_GPIO);
+			Sleep (105)
+		}
+
+		Method (_OFF, 0, NotSerialized)  // _OFF: Power Off
+		{
+			\_SB.PCI0.CTXS(CNV_BTEN);
+			\_SB.PCI0.CTXS(CNV_BT_IF_SELECT);
+			\_SB.PCI0.CTXS(BT_RESET_GPIO);
+			Sleep (105)
+		}
+
+	}
+
+	Name (_PRR, Package (0x01)  // _PRR: Power Resource for Reset
+	{
+		CTTR
+	})
+
+	Name (_PR0, Package (0x01)  // _PR0: Power Resources for D0
+	{
+		CTTR
+	})
+}
diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl
index 4f82409565..cd571ab6a8 100644
--- a/src/mainboard/google/brya/dsdt.asl
+++ b/src/mainboard/google/brya/dsdt.asl
@@ -46,4 +46,6 @@ DefinitionBlock(
 #if CONFIG(INCLUDE_NVIDIA_GPU_ASL)
 	#include "acpi/gpu_top.asl"
 #endif
+
+	#include "acpi/cnvi_bt_reset.asl"
 }