erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

nb/amd/amdk8: Link raminit_f.c

Browse source 
For this debug.c needs to be linked too.

Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19030
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans 2017-03-28 11:50:10 +02:00 • committed by Patrick Georgi
commit fb2f667da2
48 changed files with 234 additions and 192 deletions
Download patch file Download diff file Expand all files Collapse all files

8
src/mainboard/amd/dbm690t/romstage.c
View file

@ -33,22 +33,20 @@
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/early_setup.c"
#include "southbridge/amd/sb600/early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
#include <northbridge/amd/amdk8/f.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(u32 device, u32 address)
int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"

8
src/mainboard/amd/mahogany/romstage.c
View file

@ -33,17 +33,16 @@
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
#include <northbridge/amd/amdk8/f.h>
unsigned get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(u32 device, u32 address)
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
@ -51,7 +50,6 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "southbridge/amd/rs780/early_setup.c"
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"

8
src/mainboard/amd/pistachio/romstage.c
View file

@ -31,20 +31,18 @@
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/early_setup.c"
#include "southbridge/amd/sb600/early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600/early_setup.c! */
#include <northbridge/amd/amdk8/f.h>
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(u32 device, u32 address)
int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"

9
src/mainboard/amd/serengeti_cheetah/romstage.c
View file

@ -26,7 +26,7 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include <cpu/x86/bist.h>
#include <delay.h>
#include "northbridge/amd/amdk8/debug.c"
#include <cpu/amd/mtrr.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
@ -44,9 +44,9 @@ static void memreset_setup(void)
outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
int ret,i;
@ -60,7 +60,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
@ -69,7 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"

7
src/mainboard/asrock/939a785gmh/romstage.c
View file

@ -34,7 +34,6 @@
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
#include <northbridge/amd/amdk8/pre_f.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
@ -42,10 +41,10 @@
unsigned get_sbdn(unsigned bus);
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(u32 device, u32 address)
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}

8
src/mainboard/asus/a8n_e/romstage.c
View file

@ -38,7 +38,7 @@
#include <southbridge/nvidia/ck804/early_smbus.h>
#include <northbridge/amd/amdk8/raminit.h>
#include <delay.h>
#include "northbridge/amd/amdk8/debug.c"
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
@ -46,10 +46,10 @@
#include <spd.h>
#include <northbridge/amd/amdk8/pre_f.h>
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}

7
src/mainboard/asus/a8v-e_deluxe/romstage.c
View file

@ -38,7 +38,6 @@ unsigned int get_sbdn(unsigned bus);
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include <southbridge/via/vt8237r/vt8237r.h>
#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <spd.h>
@ -48,10 +47,10 @@ unsigned int get_sbdn(unsigned bus);
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}

7
src/mainboard/asus/a8v-e_se/romstage.c
View file

@ -38,7 +38,6 @@ unsigned int get_sbdn(unsigned bus);
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include <southbridge/via/vt8237r/vt8237r.h>
#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <spd.h>
@ -48,10 +47,10 @@ unsigned int get_sbdn(unsigned bus);
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}

7
src/mainboard/asus/k8v-x/romstage.c
View file

@ -38,7 +38,6 @@ unsigned int get_sbdn(unsigned bus);
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83697hf/w83697hf.h>
#include <southbridge/via/vt8237r/vt8237r.h>
#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <spd.h>
@ -46,10 +45,10 @@ unsigned int get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}

12
src/mainboard/asus/kfsn4-dre_k8/romstage.c
View file

@ -35,7 +35,7 @@ unsigned int get_sbdn(unsigned bus);
#include "northbridge/amd/amdk8/reset_test.c"
#include <cpu/x86/bist.h>
#include <delay.h>
#include "northbridge/amd/amdk8/debug.c"
#include <cpu/amd/mtrr.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627thg/w83627thg.h>
@ -44,11 +44,9 @@ unsigned int get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl);
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
@ -56,7 +54,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
@ -181,7 +178,8 @@ static const uint16_t spd_addr[] = {
RC01 | DIMM0, RC01 | DIMM2, RC01 | DIMM4, RC01 | DIMM6, RC01 | DIMM1, RC01 | DIMM3, RC01 | DIMM5, RC01 | DIMM7,
};
static void activate_spd_rom(const struct mem_controller *ctrl) {
void activate_spd_rom(const struct mem_controller *ctrl)
{
printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id);
if (ctrl->node_id == 0) {
printk(BIOS_DEBUG, "enable_spd_node0()\n");

9
src/mainboard/asus/m2n-e/romstage.c
View file

@ -36,7 +36,7 @@
#include <superio/ite/common/ite.h>
#include <superio/ite/it8716f/it8716f.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
@ -55,10 +55,10 @@ unsigned get_sbdn(unsigned bus)
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) {}
static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
void memreset(int controllers, const struct mem_controller *ctrl) {}
void activate_spd_rom(const struct mem_controller *ctrl) {}
static inline int spd_read_byte(unsigned int device, unsigned int address)
int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
@ -67,7 +67,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"

9
src/mainboard/asus/m2v-mx_se/romstage.c
View file

@ -34,7 +34,7 @@ unsigned int get_sbdn(unsigned bus);
#include <northbridge/amd/amdk8/raminit.h>
#include <delay.h>
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include <southbridge/via/vt8237r/vt8237r.h>
@ -46,10 +46,10 @@ unsigned int get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
@ -58,7 +58,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/model_fxx/init_cpus.c"

9
src/mainboard/asus/m2v/romstage.c
View file

@ -34,7 +34,7 @@ unsigned int get_sbdn(unsigned bus);
#include <northbridge/amd/amdk8/raminit.h>
#include <delay.h>
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include <southbridge/via/vt8237r/vt8237r.h>
@ -48,10 +48,10 @@ unsigned int get_sbdn(unsigned bus);
#define IT8712F_GPIO_BASE 0x0a20
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
@ -60,7 +60,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/model_fxx/init_cpus.c"

8
src/mainboard/broadcom/blast/romstage.c
View file

@ -13,7 +13,7 @@
#include <delay.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include <superio/nsc/pc87417/pc87417.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
@ -24,16 +24,16 @@
unsigned get_sbdn(unsigned bus);
static void memreset_setup(void) { }
static void memreset(int controllers, const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x71
unsigned device=(ctrl->channel0[0])>>8;
smbus_send_byte(SMBUS_HUB, device);
}
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}

9
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View file

@ -37,17 +37,17 @@
#include <superio/ite/common/ite.h>
#include <superio/ite/it8716f/it8716f.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/sis/sis966/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
@ -55,7 +55,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"

8
src/mainboard/gigabyte/m57sli/romstage.c
View file

@ -34,7 +34,6 @@
#include <superio/ite/common/ite.h>
#include <superio/ite/it8716f/it8716f.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
@ -53,10 +52,10 @@ unsigned get_sbdn(unsigned bus)
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
@ -75,7 +74,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"

8
src/mainboard/hp/dl145_g1/romstage.c
View file

@ -16,7 +16,7 @@
#include "southbridge/amd/amd8111/early_smbus.c"
#include <northbridge/amd/amdk8/raminit.h>
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <cpu/x86/bist.h>
@ -39,7 +39,7 @@ static void memreset_setup(void)
}
}
static void memreset(int controllers, const struct mem_controller *ctrl)
void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
@ -51,7 +51,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
#define SMBUS_HUB 0x18
static inline void activate_spd_rom(const struct mem_controller *ctrl)
void activate_spd_rom(const struct mem_controller *ctrl)
{
int ret,i;
unsigned device=(ctrl->channel0[0])>>8;
@ -76,7 +76,7 @@ static inline void change_i2c_mux(unsigned device)
printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret);
}
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}

9
src/mainboard/hp/dl145_g3/romstage.c
View file

@ -39,7 +39,7 @@
#include <superio/serverengines/pilot/pilot.h>
#include <superio/nsc/pc87417/pc87417.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
@ -47,9 +47,9 @@
unsigned get_sbdn(unsigned bus);
static void memreset(int controllers, const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_SWITCH1 0x70
#define SMBUS_SWITCH2 0x72
@ -58,7 +58,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
}
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
@ -67,7 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include <spd.h>
#include "cpu/amd/dualcore/dualcore.c"

8
src/mainboard/iwill/dk8_htx/romstage.c
View file

@ -12,7 +12,7 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include <cpu/x86/bist.h>
#include <delay.h>
#include "northbridge/amd/amdk8/debug.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
@ -39,7 +39,7 @@ static void memreset_setup(void)
}
}
static void memreset(int controllers, const struct mem_controller *ctrl)
void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
@ -49,9 +49,9 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
}
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}

9
src/mainboard/kontron/kt690/romstage.c
View file

@ -28,7 +28,7 @@
#include <spd.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include <cpu/amd/mtrr.h>
@ -38,17 +38,16 @@
#include "southbridge/amd/sb600/early_setup.c"
#include <northbridge/amd/amdk8/f.h>
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(u32 device, u32 address)
int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"

8
src/mainboard/msi/ms7135/romstage.c
View file

@ -35,7 +35,7 @@
#include <southbridge/nvidia/ck804/early_smbus.h>
#include <northbridge/amd/amdk8/raminit.h>
#include <delay.h>
#include "northbridge/amd/amdk8/debug.c"
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
@ -49,10 +49,10 @@
#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}

9
src/mainboard/msi/ms7260/romstage.c
View file

@ -36,7 +36,7 @@
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
@ -54,10 +54,10 @@ unsigned get_sbdn(unsigned bus)
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) {}
static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
void memreset(int controllers, const struct mem_controller *ctrl) {}
void activate_spd_rom(const struct mem_controller *ctrl) {}
static inline int spd_read_byte(unsigned int device, unsigned int address)
int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
@ -66,7 +66,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"

9
src/mainboard/msi/ms9185/romstage.c
View file

@ -35,7 +35,7 @@
#include <reset.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include <superio/nsc/pc87417/pc87417.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
@ -45,9 +45,9 @@
unsigned get_sbdn(unsigned bus);
static void memreset(int controllers, const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_SWITCH1 0x70
#define SMBUS_SWITCH2 0x72
@ -56,7 +56,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
}
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
@ -65,7 +65,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"

9
src/mainboard/msi/ms9282/romstage.c
View file

@ -32,7 +32,7 @@
#include <delay.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include <cpu/x86/bist.h>
@ -55,9 +55,9 @@ unsigned get_sbdn(unsigned bus)
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_SWITCH1 0x70
#define SMBUS_SWITCH2 0x72
@ -66,7 +66,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
}
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
@ -75,7 +75,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"

9
src/mainboard/nvidia/l1_2pvv/romstage.c
View file

@ -35,7 +35,7 @@
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
@ -53,10 +53,10 @@ unsigned get_sbdn(unsigned bus)
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
@ -65,7 +65,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"

8
src/mainboard/siemens/sitemp_g1p1/romstage.c
View file

@ -40,31 +40,29 @@
#include "southbridge/amd/rs690/early_setup.c"
#include "southbridge/amd/sb600/early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
#include <northbridge/amd/amdk8/f.h>
#define SERIAL_DEV PNP_DEV(0x2e, CONFIG_UART_FOR_CONSOLE == 1 ? IT8712F_SP2 : IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
static void memreset(int controllers, const struct mem_controller *ctrl)
void memreset(int controllers, const struct mem_controller *ctrl)
{
}
/* called in raminit_f.c */
static inline void activate_spd_rom(const struct mem_controller *ctrl)
void activate_spd_rom(const struct mem_controller *ctrl)
{
}
/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"

8
src/mainboard/sunw/ultra40/romstage.c
View file

@ -15,7 +15,7 @@
#include <delay.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include <superio/smsc/lpc47b397/lpc47b397.h>
#include <cpu/x86/bist.h>
#include "superio/smsc/lpc47b397/early_gpio.c"
@ -26,7 +26,7 @@
#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
#define SUPERIO_GPIO_IO_BASE 0x400
static void memreset(int controllers, const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
#ifdef ENABLE_ONBOARD_SCSI
static void sio_gpio_setup(void)
@ -40,9 +40,9 @@ static void sio_gpio_setup(void)
}
#endif
static inline void activate_spd_rom(const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}

9
src/mainboard/sunw/ultra40m2/romstage.c
View file

@ -34,7 +34,7 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/smsc/dme1737/dme1737.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1)
@ -52,10 +52,10 @@ unsigned get_sbdn(unsigned bus)
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
@ -64,7 +64,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"

9
src/mainboard/supermicro/h8dme/romstage.c
View file

@ -32,7 +32,7 @@
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -51,9 +51,9 @@ unsigned get_sbdn(unsigned bus)
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
void activate_spd_rom(const struct mem_controller *ctrl)
{
#if 0
/* We don't do any switching yet. */
@ -65,7 +65,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
#endif
}
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
@ -74,7 +74,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"

9
src/mainboard/supermicro/h8dmr/romstage.c
View file

@ -35,7 +35,7 @@
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -54,10 +54,10 @@ unsigned get_sbdn(unsigned bus)
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
@ -66,7 +66,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"

9
src/mainboard/technexion/tim5690/romstage.c
View file

@ -27,7 +27,7 @@
#include <spd.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include <cpu/x86/bist.h>
@ -38,17 +38,16 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(u32 device, u32 address)
int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"

9
src/mainboard/technexion/tim8690/romstage.c
View file

@ -27,7 +27,7 @@
#include <spd.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include <cpu/x86/bist.h>
@ -39,17 +39,16 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(u32 device, u32 address)
int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"

9
src/mainboard/tyan/s2912/romstage.c
View file

@ -35,7 +35,7 @@
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -53,10 +53,10 @@ unsigned get_sbdn(unsigned bus)
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
@ -65,7 +65,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"

7
src/mainboard/winent/mb6047/romstage.c
View file

@ -15,7 +15,6 @@
#include <delay.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627thg/w83627thg.h>
#include <cpu/x86/bist.h>
@ -25,10 +24,10 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
static void memreset_setup(void) { }
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}