CAR patch from YH LU
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
872141a402
commit
fb0a64ba77
12 changed files with 329 additions and 359 deletions
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@ -8,10 +8,17 @@
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/* Save the BIST result */
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movl %eax, %ebp
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// for normal part %ebx already contain cpu_init_detected from fallback call
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CacheAsRam:
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/* hope we can skip the double set for normal part */
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#if USE_FALLBACK_IMAGE == 1
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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andl $0x00000800, %eax
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movl %eax, %ebx ; // We store the status about if cpu_init_detected
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/* Set MtrrFixDramModEn for clear fixed mtrr */
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xorl %eax, %eax # clear %eax and %edx
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@ -53,7 +60,6 @@ clear_fixed_var_mtrr_out:
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orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
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wrmsr
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#if 1
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#if CacheSize == 0x10000
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/* enable caching for 64K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c0000*/
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@ -86,30 +92,6 @@ clear_fixed_var_mtrr_out:
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xorl %eax, %eax
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wrmsr
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#else
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/* enable caching for 64K using variable mtrr */
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movl $0x200, %ecx
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xorl %edx, %edx
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movl $(CacheBase | MTRR_TYPE_WRBACK), %eax
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wrmsr
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movl $0x201, %ecx
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movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
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movl $((~((CacheBase + CacheSize) - 1)) | 0x800), %eax
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wrmsr
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/* make it to be IO by clearing RD Dram and WR Dram */
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movl $IORR0_BASE, %ecx
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xorl %edx, %edx
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movl $CacheBase, %eax /* bit 3, and bit 4 = 0 mean clear RD ram and WR ram */
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wrmsr
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movl $IORR0_MASK, %ecx
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movl $0x000000ff, %edx
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movl $(~((CacheBase + CacheSize) - 1) | 0x800), %eax
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wrmsr
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#endif
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/* enable memory access for 0 - 1MB using top_mem */
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movl $TOP_MEM, %ecx
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xorl %edx, %edx
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@ -145,7 +127,6 @@ clear_fixed_var_mtrr_out:
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#if USE_FALLBACK_IMAGE == 1
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/* Read the range with lodsl*/
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movl $(CacheBase+CacheSize-4), %esi
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std
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@ -157,36 +138,6 @@ clear_fixed_var_mtrr_out:
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xorl %eax, %eax
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rep stosl
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#if 0
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/* check the cache as ram */
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movl $CacheBase, %esi
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movl $(CacheSize>>2), %ecx
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.xin1:
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movl %esi, %eax
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movl %eax, (%esi)
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movl $0x1000, %edx
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movb %ah, %al
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.testx1:
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outb %al, $0x80
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decl %edx
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jnz .testx1
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movl (%esi), %eax
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cmpb 0xff, %al
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je .xin2 /* dont show */
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movl $0x1000, %edx
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.testx2:
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outb %al, $0x80
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decl %edx
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jnz .testx2
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.xin2: decl %ecx
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je .xout1
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add $4, %esi
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jmp .xin1
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.xout1:
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#endif
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#endif /*USE_FALLBACK_IMAGE == 1*/
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@ -198,6 +149,7 @@ clear_fixed_var_mtrr_out:
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movl %ebp, %eax
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/* We need to set ebp ? No need */
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movl %esp, %ebp
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pushl %ebx /* init detected */
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pushl %eax /* bist */
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call amd64_main
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/* We will not go back */
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@ -1,95 +0,0 @@
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/* by yhlu 6.2005 */
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/* be warned, this file will be used other cores and core0/node0 */
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__asm__ volatile (
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/*
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FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
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It is only needed if we want to go back
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*/
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/* We don't need cache as ram for now on */
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/* disable cache */
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"movl %cr0, %eax\n\t"
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"orl $(0x1<<30),%eax\n\t"
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"movl %eax, %cr0\n\t"
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/* clear sth */
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"movl $0x269, %ecx\n\t" /* fix4k_c8000*/
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"xorl %edx, %edx\n\t"
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"xorl %eax, %eax\n\t"
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"wrmsr\n\t"
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#if DCACHE_RAM_SIZE > 0x8000
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"movl $0x268, %ecx\n\t" /* fix4k_c0000*/
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"wrmsr\n\t"
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#endif
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/* disable fixed mtrr from now on, it will be enabled by linuxbios_ram again*/
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"movl $0xC0010010, %ecx\n\t"
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// "movl $SYSCFG_MSR, %ecx\n\t"
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"rdmsr\n\t"
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"andl $(~(3<<18)), %eax\n\t"
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// "andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
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"wrmsr\n\t"
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/* Set the default memory type and disable fixed and enable variable MTRRs */
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"movl $0x2ff, %ecx\n\t"
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// "movl $MTRRdefType_MSR, %ecx\n\t"
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"xorl %edx, %edx\n\t"
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/* Enable Variable and Disable Fixed MTRRs */
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"movl $0x00000800, %eax\n\t"
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"wrmsr\n\t"
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#if defined(CLEAR_FIRST_1M_RAM)
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/* enable caching for first 1M using variable mtrr */
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"movl $0x200, %ecx\n\t"
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"xorl %edx, %edx\n\t"
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"movl $(0 | 1), %eax\n\t"
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// "movl $(0 | MTRR_TYPE_WRCOMB), %eax\n\t"
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"wrmsr\n\t"
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"movl $0x201, %ecx\n\t"
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"movl $0x0000000f, %edx\n\t"
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"movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
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"wrmsr\n\t"
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#endif
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/* enable cache */
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"movl %cr0, %eax\n\t"
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"andl $0x9fffffff,%eax\n\t"
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"movl %eax, %cr0\n\t"
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#if defined(CLEAR_FIRST_1M_RAM)
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/* clear the first 1M */
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"movl $0x0, %edi\n\t"
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"cld\n\t"
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"movl $(0x100000>>2), %ecx\n\t"
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"xorl %eax, %eax\n\t"
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"rep stosl\n\t"
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/* disable cache */
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"movl %cr0, %eax\n\t"
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"orl $(0x1<<30),%eax\n\t"
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"movl %eax, %cr0\n\t"
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/* enable caching for first 1M using variable mtrr */
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"movl $0x200, %ecx\n\t"
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"xorl %edx, %edx\n\t"
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"movl $(0 | 6), %eax\n\t"
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// "movl $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
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"wrmsr\n\t"
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"movl $0x201, %ecx\n\t"
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"movl $0x0000000f, %edx\n\t"
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"movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
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"wrmsr\n\t"
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/* enable cache */
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"movl %cr0, %eax\n\t"
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"andl $0x9fffffff,%eax\n\t"
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"movl %eax, %cr0\n\t"
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"invd\n\t"
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/*
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FIXME: I hope we don't need to change esp and ebp value here, so we can restore value from mmx sse back
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But the problem is the range is some io related, So don't go back
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*/
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#endif
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);
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53
src/cpu/amd/car/clear_1m_ram.c
Normal file
53
src/cpu/amd/car/clear_1m_ram.c
Normal file
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@ -0,0 +1,53 @@
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/* by yhlu 6.2005 */
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/* be warned, this file will be used core 0/node 0 only */
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__asm__ volatile (
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/* disable cache */
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"movl %cr0, %eax\n\t"
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"orl $(0x1<<30),%eax\n\t"
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"movl %eax, %cr0\n\t"
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/* enable caching for first 1M using variable mtrr */
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"movl $0x200, %ecx\n\t"
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"xorl %edx, %edx\n\t"
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"movl $(0 | 1), %eax\n\t"
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// "movl $(0 | MTRR_TYPE_WRCOMB), %eax\n\t"
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"wrmsr\n\t"
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"movl $0x201, %ecx\n\t"
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"movl $0x0000000f, %edx\n\t"
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"movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
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"wrmsr\n\t"
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/* clear the first 1M */
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"movl $0x0, %edi\n\t"
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"cld\n\t"
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"movl $(0x100000>>2), %ecx\n\t"
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"xorl %eax, %eax\n\t"
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"rep stosl\n\t"
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/* disable cache */
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"movl %cr0, %eax\n\t"
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"orl $(0x1<<30),%eax\n\t"
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"movl %eax, %cr0\n\t"
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/* enable caching for first 1M using variable mtrr */
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"movl $0x200, %ecx\n\t"
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"xorl %edx, %edx\n\t"
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"movl $(0 | 6), %eax\n\t"
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// "movl $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
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"wrmsr\n\t"
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"movl $0x201, %ecx\n\t"
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"movl $0x0000000f, %edx\n\t"
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"movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
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"wrmsr\n\t"
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/* enable cache */
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"movl %cr0, %eax\n\t"
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"andl $0x9fffffff,%eax\n\t"
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"movl %eax, %cr0\n\t"
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"invd\n\t"
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);
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46
src/cpu/amd/car/disable_cache_as_ram.c
Normal file
46
src/cpu/amd/car/disable_cache_as_ram.c
Normal file
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@ -0,0 +1,46 @@
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/* by yhlu 6.2005 */
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/* be warned, this file will be used other cores and core 0 / node 0 */
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__asm__ volatile (
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/*
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FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
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It is only needed if we want to go back
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*/
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/* We don't need cache as ram for now on */
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/* disable cache */
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"movl %cr0, %eax\n\t"
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"orl $(0x1<<30),%eax\n\t"
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"movl %eax, %cr0\n\t"
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/* clear sth */
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"movl $0x269, %ecx\n\t" /* fix4k_c8000*/
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"xorl %edx, %edx\n\t"
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"xorl %eax, %eax\n\t"
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"wrmsr\n\t"
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#if DCACHE_RAM_SIZE > 0x8000
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"movl $0x268, %ecx\n\t" /* fix4k_c0000*/
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"wrmsr\n\t"
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#endif
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/* disable fixed mtrr from now on, it will be enabled by linuxbios_ram again*/
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"movl $0xC0010010, %ecx\n\t"
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// "movl $SYSCFG_MSR, %ecx\n\t"
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"rdmsr\n\t"
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"andl $(~(3<<18)), %eax\n\t"
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// "andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
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"wrmsr\n\t"
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/* Set the default memory type and disable fixed and enable variable MTRRs */
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"movl $0x2ff, %ecx\n\t"
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// "movl $MTRRdefType_MSR, %ecx\n\t"
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"xorl %edx, %edx\n\t"
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/* Enable Variable and Disable Fixed MTRRs */
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"movl $0x00000800, %eax\n\t"
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"wrmsr\n\t"
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/* enable cache */
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"movl %cr0, %eax\n\t"
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"andl $0x9fffffff,%eax\n\t"
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"movl %eax, %cr0\n\t"
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);
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81
src/cpu/amd/car/post_cache_as_ram.c
Normal file
81
src/cpu/amd/car/post_cache_as_ram.c
Normal file
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@ -0,0 +1,81 @@
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static void post_cache_as_ram(unsigned cpu_reset)
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{
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#if 1
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{
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/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
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unsigned v_esp;
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__asm__ volatile (
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"movl %%esp, %0\n\t"
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: "=a" (v_esp)
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);
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#if CONFIG_USE_INIT
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printk_debug("v_esp=%08x\r\n", v_esp);
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#else
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print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
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#endif
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}
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#endif
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#if CONFIG_USE_INIT
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printk_debug("cpu_reset = %08x\r\n",cpu_reset);
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#else
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print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
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#endif
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if(cpu_reset == 0) {
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print_debug("Clearing initial memory region: ");
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}
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print_debug("No cache as ram now - ");
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/* store cpu_reset to ebx */
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__asm__ volatile (
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"movl %0, %%ebx\n\t"
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::"a" (cpu_reset)
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);
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#include "cpu/amd/car/disable_cache_as_ram.c"
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if(cpu_reset==0) { // cpu_reset don't need to clear it
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#include "cpu/amd/car/clear_1m_ram.c"
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}
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__asm__ volatile (
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/* set new esp */ /* before _RAMBASE */
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"subl %0, %%ebp\n\t"
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"subl %0, %%esp\n\t"
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::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
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);
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{
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unsigned new_cpu_reset;
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/* get back cpu_reset from ebx */
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__asm__ volatile (
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"movl %%ebx, %0\n\t"
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:"=a" (new_cpu_reset)
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);
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print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
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if(new_cpu_reset==0) {
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print_debug("done\r\n");
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} else
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{
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print_debug("\r\n");
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}
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#if CONFIG_USE_INIT
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printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
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#else
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print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
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#endif
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/*copy and execute linuxbios_ram */
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copy_and_run(new_cpu_reset);
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/* We will not return */
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}
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print_debug("should not be here -\r\n");
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}
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