diff --git a/src/cpu/ev6/Config b/src/cpu/ev6/Config new file mode 100644 index 0000000000..f964cfc0c2 --- /dev/null +++ b/src/cpu/ev6/Config @@ -0,0 +1,2 @@ +makedefine CPU_OPT=-mcpu=ev6 -Wa,-m21264 +option USE_CPU_EV6=1 diff --git a/src/cpu/ev6/dc21264.h b/src/cpu/ev6/dc21264.h index bb1016feb3..c29ff92356 100644 --- a/src/cpu/ev6/dc21264.h +++ b/src/cpu/ev6/dc21264.h @@ -55,7 +55,7 @@ #define EV6_SCB__DTB_TAG1 ((1 << 1) | (1 << 5)) #define EV6_SCB__DTB_PTE0 ((1 << 0) | (1 << 4)) #define EV6_SCB__DTB_PTE1 ((1 << 3) | (1 << 7)) -#define EV6_SCB__DTB_ALTMODE (1 << 6) +#define EV6_SCB__DTB_ALT_MODE (1 << 6) #define EV6_SCB__DTB_IAP (1 << 7) #define EV6_SCB__DTB_IA (1 << 7) #define EV6_SCB__DTB_IS0 (1 << 6) @@ -80,7 +80,7 @@ * ========================================================= */ #define EV6__CC ((0xC0 << 8) | EV6_SCB__CC) -#define EV6__CTL ((0xC1 << 8) | EV6_SCB__CTL) +#define EV6__CC_CTL ((0xC1 << 8) | EV6_SCB__CC_CTL) #define EV6__VA ((0xC2 << 8) | EV6_SCB__VA) #define EV6__VA_CTL ((0xC4 << 8) | EV6_SCB__VA_CTL) #define EV6__VA_FORM ((0xC3 << 8) | EV6_SCB__VA_FORM) @@ -121,7 +121,7 @@ #define EV6__DTB_TAG1 ((0xA0 << 8) | EV6_SCB__DTB_TAG1) #define EV6__DTB_PTE0 ((0x21 << 8) | EV6_SCB__DTB_PTE0) #define EV6__DTB_PTE1 ((0xA1 << 8) | EV6_SCB__DTB_PTE1) -#define EV6__DTB_ALTMODE ((0x26 << 8) | EV6_SCB__DTB_ALTMODE) +#define EV6__DTB_ALT_MODE ((0x26 << 8) | EV6_SCB__DTB_ALT_MODE) #define EV6__DTB_IAP ((0xA2 << 8) | EV6_SCB__DTB_IAP) #define EV6__DTB_IA ((0xA3 << 8) | EV6_SCB__DTB_IA) #define EV6__DTB_IS0 ((0x24 << 8) | EV6_SCB__DTB_IS0) @@ -420,6 +420,14 @@ #define EV6__I_CTL__VPTB__V 18 #define EV6__I_CTL__VPTB__M ((1 << EV6__I_CTL__VPTB__V) -1) +/* EV6__I_STAT */ +#define EV6__I_STAT__TPE__S 29 +#define EV6__I_STAT__TPE__V 1 +#define EV6__I_STAT__TPE__M ((1 << EV6__I_STAT__TPE__V) -1) +#define EV6__I_STAT__DPE__S 30 +#define EV6__I_STAT__DPE__V 1 +#define EV6__I_STAT__DPE__M ((1 << EV6__I_STAT__DPE__V) -1) + /* EV6__IC_FLUSH (no subfields) */ /* EV6__IC_FLUSH_ASM (no subfields) */ /* EV6__CLR_MAP (no subfields */ @@ -634,4 +642,199 @@ /* EV6__C_DATA (no subfields) */ /* EV6__C_SHIFT (no subfields) */ -#endif /* DC21264_H */ +/* + * Palcode entry points + * ========================================================= + */ + +/* Exception pal entry points */ +#define EV6__DTBM_DOUBLE_3_ENTRY 0x100 +#define EV6__DTBM_DOUBLE_4_ENTRY 0x180 +#define EV6__FEN_ENTRY 0x200 +#define EV6__UNALIGN_ENTRY 0x280 +#define EV6__DTBM_SINGLE_ENTRY 0x300 +#define EV6__DFAULT_ENTRY 0x380 +#define EV6__OPCDEC_ENTRY 0x400 +#define EV6__IACV_ENTRY 0x480 +#define EV6__MCHK_ENTRY 0x500 +#define EV6__ITB_MISS_ENTRY 0x580 +#define EV6__ARITH_ENTRY 0x600 +#define EV6__INTERRUPT_ENTRY 0x680 +#define EV6__MT_FPCR_ENTRY 0x700 +#define EV6__RESET_ENTRY 0x780 +/* Privelidged pal entry points */ +#define EV6__CALL_PAL_00_ENTRY 0x2000 /* aka Halt */ +#define EV6__CALL_PAL_01_ENTRY 0x2040 +#define EV6__CALL_PAL_02_ENTRY 0x2080 +#define EV6__CALL_PAL_03_ENTRY 0x20C0 +#define EV6__CALL_PAL_04_ENTRY 0x2100 +#define EV6__CALL_PAL_05_ENTRY 0x2140 +#define EV6__CALL_PAL_06_ENTRY 0x2180 +#define EV6__CALL_PAL_07_ENTRY 0x21C0 +#define EV6__CALL_PAL_08_ENTRY 0x2200 +#define EV6__CALL_PAL_09_ENTRY 0x2240 +#define EV6__CALL_PAL_0A_ENTRY 0x2280 +#define EV6__CALL_PAL_0B_ENTRY 0x22C0 +#define EV6__CALL_PAL_0C_ENTRY 0x2300 +#define EV6__CALL_PAL_0D_ENTRY 0x2340 +#define EV6__CALL_PAL_0E_ENTRY 0x2380 +#define EV6__CALL_PAL_0F_ENTRY 0x23C0 +#define EV6__CALL_PAL_10_ENTRY 0x2400 +#define EV6__CALL_PAL_11_ENTRY 0x2440 +#define EV6__CALL_PAL_12_ENTRY 0x2480 +#define EV6__CALL_PAL_13_ENTRY 0x24C0 +#define EV6__CALL_PAL_14_ENTRY 0x2500 +#define EV6__CALL_PAL_15_ENTRY 0x2540 +#define EV6__CALL_PAL_16_ENTRY 0x2580 +#define EV6__CALL_PAL_17_ENTRY 0x25C0 +#define EV6__CALL_PAL_18_ENTRY 0x2600 +#define EV6__CALL_PAL_19_ENTRY 0x2640 +#define EV6__CALL_PAL_1A_ENTRY 0x2680 +#define EV6__CALL_PAL_1B_ENTRY 0x26C0 +#define EV6__CALL_PAL_1C_ENTRY 0x2700 +#define EV6__CALL_PAL_1D_ENTRY 0x2740 +#define EV6__CALL_PAL_1E_ENTRY 0x2780 +#define EV6__CALL_PAL_1F_ENTRY 0x27C0 +#define EV6__CALL_PAL_20_ENTRY 0x2800 +#define EV6__CALL_PAL_21_ENTRY 0x2840 +#define EV6__CALL_PAL_22_ENTRY 0x2880 +#define EV6__CALL_PAL_23_ENTRY 0x28C0 +#define EV6__CALL_PAL_24_ENTRY 0x2900 +#define EV6__CALL_PAL_25_ENTRY 0x2940 +#define EV6__CALL_PAL_26_ENTRY 0x2980 +#define EV6__CALL_PAL_27_ENTRY 0x29C0 +#define EV6__CALL_PAL_28_ENTRY 0x2A00 +#define EV6__CALL_PAL_29_ENTRY 0x2A40 +#define EV6__CALL_PAL_2A_ENTRY 0x2A80 +#define EV6__CALL_PAL_2B_ENTRY 0x2AC0 +#define EV6__CALL_PAL_2C_ENTRY 0x2B00 +#define EV6__CALL_PAL_2D_ENTRY 0x2B40 +#define EV6__CALL_PAL_2E_ENTRY 0x2B80 +#define EV6__CALL_PAL_2F_ENTRY 0x2BC0 +#define EV6__CALL_PAL_30_ENTRY 0x2C00 +#define EV6__CALL_PAL_31_ENTRY 0x2C40 +#define EV6__CALL_PAL_32_ENTRY 0x2C80 +#define EV6__CALL_PAL_33_ENTRY 0x2CC0 +#define EV6__CALL_PAL_34_ENTRY 0x2D00 +#define EV6__CALL_PAL_35_ENTRY 0x2D40 +#define EV6__CALL_PAL_36_ENTRY 0x2D80 +#define EV6__CALL_PAL_37_ENTRY 0x2DC0 +#define EV6__CALL_PAL_38_ENTRY 0x2E00 +#define EV6__CALL_PAL_39_ENTRY 0x2E40 +#define EV6__CALL_PAL_3A_ENTRY 0x2E80 +#define EV6__CALL_PAL_3B_ENTRY 0x2EC0 +#define EV6__CALL_PAL_3C_ENTRY 0x2F00 +#define EV6__CALL_PAL_3D_ENTRY 0x2F40 +#define EV6__CALL_PAL_3E_ENTRY 0x2F80 +#define EV6__CALL_PAL_3F_ENTRY 0x2FC0 +/* Unpriveledged pal entry points */ +#define EV6__CALL_PAL_80_ENTRY 0x3000 +#define EV6__CALL_PAL_81_ENTRY 0x3040 +#define EV6__CALL_PAL_82_ENTRY 0x3080 +#define EV6__CALL_PAL_83_ENTRY 0x30C0 +#define EV6__CALL_PAL_84_ENTRY 0x3100 +#define EV6__CALL_PAL_85_ENTRY 0x3140 +#define EV6__CALL_PAL_86_ENTRY 0x3180 +#define EV6__CALL_PAL_87_ENTRY 0x31C0 +#define EV6__CALL_PAL_88_ENTRY 0x3200 +#define EV6__CALL_PAL_89_ENTRY 0x3240 +#define EV6__CALL_PAL_8A_ENTRY 0x3280 +#define EV6__CALL_PAL_8B_ENTRY 0x32C0 +#define EV6__CALL_PAL_8C_ENTRY 0x3300 +#define EV6__CALL_PAL_8D_ENTRY 0x3340 +#define EV6__CALL_PAL_8E_ENTRY 0x3380 +#define EV6__CALL_PAL_8F_ENTRY 0x33C0 +#define EV6__CALL_PAL_90_ENTRY 0x3400 +#define EV6__CALL_PAL_91_ENTRY 0x3440 +#define EV6__CALL_PAL_92_ENTRY 0x3480 +#define EV6__CALL_PAL_93_ENTRY 0x34C0 +#define EV6__CALL_PAL_94_ENTRY 0x3500 +#define EV6__CALL_PAL_95_ENTRY 0x3540 +#define EV6__CALL_PAL_96_ENTRY 0x3580 +#define EV6__CALL_PAL_97_ENTRY 0x35C0 +#define EV6__CALL_PAL_98_ENTRY 0x3600 +#define EV6__CALL_PAL_99_ENTRY 0x3640 +#define EV6__CALL_PAL_9A_ENTRY 0x3680 +#define EV6__CALL_PAL_9B_ENTRY 0x36C0 +#define EV6__CALL_PAL_9C_ENTRY 0x3700 +#define EV6__CALL_PAL_9D_ENTRY 0x3740 +#define EV6__CALL_PAL_9E_ENTRY 0x3780 +#define EV6__CALL_PAL_9F_ENTRY 0x37C0 +#define EV6__CALL_PAL_A0_ENTRY 0x3800 +#define EV6__CALL_PAL_A1_ENTRY 0x3840 +#define EV6__CALL_PAL_A2_ENTRY 0x3880 +#define EV6__CALL_PAL_A3_ENTRY 0x38C0 +#define EV6__CALL_PAL_A4_ENTRY 0x3900 +#define EV6__CALL_PAL_A5_ENTRY 0x3940 +#define EV6__CALL_PAL_A6_ENTRY 0x3980 +#define EV6__CALL_PAL_A7_ENTRY 0x39C0 +#define EV6__CALL_PAL_A8_ENTRY 0x3A00 +#define EV6__CALL_PAL_A9_ENTRY 0x3A40 +#define EV6__CALL_PAL_AA_ENTRY 0x3A80 +#define EV6__CALL_PAL_AB_ENTRY 0x3AC0 +#define EV6__CALL_PAL_AC_ENTRY 0x3B00 +#define EV6__CALL_PAL_AD_ENTRY 0x3B40 +#define EV6__CALL_PAL_AE_ENTRY 0x3B80 +#define EV6__CALL_PAL_AF_ENTRY 0x3BC0 +#define EV6__CALL_PAL_B0_ENTRY 0x3C00 +#define EV6__CALL_PAL_B1_ENTRY 0x3C40 +#define EV6__CALL_PAL_B2_ENTRY 0x3C80 +#define EV6__CALL_PAL_B3_ENTRY 0x3CC0 +#define EV6__CALL_PAL_B4_ENTRY 0x3D00 +#define EV6__CALL_PAL_B5_ENTRY 0x3D40 +#define EV6__CALL_PAL_B6_ENTRY 0x3D80 +#define EV6__CALL_PAL_B7_ENTRY 0x3DC0 +#define EV6__CALL_PAL_B8_ENTRY 0x3E00 +#define EV6__CALL_PAL_B9_ENTRY 0x3E40 +#define EV6__CALL_PAL_BA_ENTRY 0x3E80 +#define EV6__CALL_PAL_BB_ENTRY 0x3EC0 +#define EV6__CALL_PAL_BC_ENTRY 0x3F00 +#define EV6__CALL_PAL_BD_ENTRY 0x3F40 +#define EV6__CALL_PAL_BE_ENTRY 0x3F80 +#define EV6__CALL_PAL_BF_ENTRY 0x3FC0 +/* All other pall call entry points are handled by OPCDEC entry */ + + +/* Alpha Logical Register Definitions + * ========================================================= + */ + +/* PAL Shadow Registers */ +#define p0 $4 +#define p1 $5 +#define p2 $6 +#define p3 $7 +#define p4 $20 +#define p5 $21 +#define p6 $22 +#define p7 $23 + +/* Alpha Logical Instruction Definitions + * ========================================================= + */ + +#define mtpr hw_mtpr +#define mfpr hw_mfpr + +#define ldl_p hw_ldl/p +#define ldq_p hw_ldq/p +#define stl_p hw_stl/p +#define stq_p hw_stq/p + +/* Virtual PTE fetch variants of HW_LD. + */ +#define ld_vpte hw_ldq/v + +/* + * Physical mode load-lock and store-conditional variants of + * HW_LD and HW_ST. + */ +#define ldq_lp hw_ldq/pl +#define stq_cp hw_stq/pc + +#define STALL bis $31, $31, $31 + +/* Align the code to a hardware fetch block */ +#define FETCH_BLOCK_ALIGN .p2alignl 4, 0x47ff041f + +#endif /* DC21264_H */ diff --git a/src/cpu/ev6/start.inc b/src/cpu/ev6/start.inc new file mode 100644 index 0000000000..ce359d0d88 --- /dev/null +++ b/src/cpu/ev6/start.inc @@ -0,0 +1,469 @@ +#include +#include +#include +.set noat +.set noreorder +.text + +#define PAL_EXCEPT(label,location) . = location ; label: +#define PAL_EXCEPT_DUMMY(location) . = location ; mb ; mb ; mb; hw_mfpr p7, EV6__EXC_ADDR ; bsr p0, __fatal_error_pal; mb ; mb ; mb +#define PAL_CALL_DUMMY(location) . = location ; mb ; mb ; mb ; mb ; bsr p0, __fatal_error_pal ; mb ; mb ; mb + +#define va_48 0 +#define mchk_en 1 +#define tb_mb_en 0 + +#define EV6__I_STAT__W1C ((1 << EV6__I_STAT__TPE__S) | (1 << EV6__I_STAT__DPE__S)) +#define EV6__DC_STAT__W1C ( \ + (1 << EV6__DC_STAT__TPERR_P0__S) | \ + (1 << EV6__DC_STAT__TPERR_P1__S) | \ + (1 << EV6__DC_STAT__ECC_ERR_ST__S) | \ + (1 << EV6__DC_STAT__ECC_ERR_LD__S) | \ + (1 << EV6__DC_STAT__SEO__S)) + +#define EV6__I_CTL__INIT (\ + (3 << EV6__I_CTL__IC_EN__S) | \ + (2 << (EV6__I_CTL__SPE__S + va_48)) | \ + (2 << EV6__I_CTL__SDE__S) | \ + (3 << EV6__I_CTL__SBE__S) | \ + (va_48 << EV6__I_CTL__VA_48__S) | \ + (1 << EV6__I_CTL__CALL_PAL_R23__S) | \ + (mchk_en << EV6__I_CTL__MCHK_EN__S) | \ + (tb_mb_en << EV6__I_CTL__TB_MB_EN__S)) + +#define EV6__PCTX__INIT (1 << EV6__PCTX__FPE__S) + +#define EV6__M_CTL__INIT (2 << (EV6__M_CTL__SPE__S+va_48)) + +#define EV6__IER__INIT 0 + +#define EV6__HW_INT_CLR__INIT ( \ + (1 << (EV6__HW_INT_CLR__MCHK_D__S - EV6__HW_INT_CLR__MCHK_D__S)) | \ + (3 << (EV6__HW_INT_CLR__PC__S - EV6__HW_INT_CLR__MCHK_D__S)) | \ + (1 << (EV6__HW_INT_CLR__CR__S - EV6__HW_INT_CLR__MCHK_D__S)) | \ + (1 << (EV6__HW_INT_CLR__SL__S - EV6__HW_INT_CLR__MCHK_D__S))) + +#define EV6__VA_CTL__INIT (va_48 << EV6__VA_CTL__VA_48__S) + +EntryPoint: + /* On startup + * R19 - Signature (0xDEC?????) likely (0xDECB001) + * R23 - Memory size in bytes. + * r22 - CPU speed in picoseconds. + * R25 - Chip revision. + * excAddr - Address of ICache flush code to execute in PALmode. + */ + + /* Palcode switching entry point */ + mb + bis a3, a3, a0 /* Signature */ + bis t9, t9, a1 /* Memory size in bytes */ + bis t8, t8, a2 /* CPU speed in picoseconds */ + br zero, pal_mode_start + mb + mb + mb + +PAL_EXCEPT_DUMMY(EV6__DTBM_DOUBLE_3_ENTRY) +PAL_EXCEPT_DUMMY(EV6__DTBM_DOUBLE_4_ENTRY) +PAL_EXCEPT_DUMMY(EV6__FEN_ENTRY) +PAL_EXCEPT_DUMMY(EV6__UNALIGN_ENTRY) + + /* DTBM */ +PAL_EXCEPT(DTBM_SINGLE, EV6__DTBM_SINGLE_ENTRY) + hw_mfpr p7, EV6__EXC_ADDR /* (0L,1) get exception address */ + hw_mfpr p2, EV6__VA /* (4-7,1L,3) get original va */ + + lda p1, 0x3301(zero) /* all r/w enable */ + srl p2, 13, p0 /* shift out the byte offset */ + sll p0, EV6__DTB_PTE0__PFN__S, p0 /* get pfn into position */ + bis p0, p1, p0 /* produce the pte */ + + FETCH_BLOCK_ALIGN + hw_mtpr p2, EV6__DTB_TAG0 /* (2&6,0L) write tag0 */ + hw_mtpr p2, EV6__DTB_TAG1 /* (1&5,1L) write tag1 */ + hw_mtpr p0, EV6__DTB_PTE0 /* (0,4,2,6) (0L) write pte0 */ + hw_mtpr p0, EV6__DTB_PTE1 /* (3,7,1,5) (1L) write pte1 */ + + hw_mtpr zero, EV6__MM_STAT /* (4-7,0L) start outside IQ */ + FETCH_BLOCK_ALIGN + hw_ret (p7) /* return with jmp */ + br zero, .-4 /* stop predictor */ + +PAL_EXCEPT_DUMMY(EV6__DFAULT_ENTRY) +PAL_EXCEPT_DUMMY(EV6__OPCDEC_ENTRY) +PAL_EXCEPT_DUMMY(EV6__IACV_ENTRY) +PAL_EXCEPT_DUMMY(EV6__MCHK_ENTRY) + + /* *ITBM* */ +PAL_EXCEPT(ITB_MISS, EV6__ITB_MISS_ENTRY) + hw_mfpr p7, EV6__EXC_ADDR /* (0L,1) get exception address */ + srl p7, 13, p2 /* shift out the byte offset */ + lda p1, 0x301(zero) /* all read enable */ + sll p2, EV6__ITB_PTE__PFN__S, p2 /* get pfn into position */ + bis p2, p1, p2 /* produce the pte */ + + FETCH_BLOCK_ALIGN + hw_mtpr p7, EV6__ITB_TAG /* (2&6,0L) write tag0 */ + hw_mtpr p2, EV6__ITB_PTE /* (0&4,0L) write pte0 */ + FETCH_BLOCK_ALIGN + hw_ret/stall (p7) /* (0L) return */ + br zero, .-4 + +PAL_EXCEPT_DUMMY(EV6__ARITH_ENTRY) +PAL_EXCEPT_DUMMY(EV6__INTERRUPT_ENTRY) +PAL_EXCEPT_DUMMY(EV6__MT_FPCR_ENTRY) +PAL_EXCEPT_DUMMY(EV6__RESET_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_00_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_01_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_02_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_03_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_04_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_05_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_06_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_07_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_08_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_09_ENTRY) + +#if 0 +PAL_CALL_DUMMY(EV6__CALL_PAL_0A_ENTRY) +#else + /* swppal */ +PAL_EXCEPT(SWPPAL, EV6__CALL_PAL_0A_ENTRY) +#define OSF_P_MISC__SWITCH__S 62 + /* new pal base is in a0 */ + bis a0, a0, p1 /* base in p1 */ + lda p0, 0x7fff(zero) /* check for pal base */ + and p1, p0, p0 /* get low 15 bits */ + cmpeq p0, 0, v0 /* check for non-zero bits */ + + blbc v0, call_pal__swppal_fail /* if not clear say unknown */ + + bis zero, 1, p0 /* get a '1' */ + sll p0, OSF_P_MISC__SWITCH__S, p0 /* switch bit into position */ + bis zero, p0, p6 /* mark switch */ + + bis zero, zero, v0 /* status success */ + bis p1, 1, p1 /* set pal mode bit */ + hw_ret (p1) /* go to it */ + bis zero, zero, zero /* nop */ + +call_pal__swppal_fail: + bis zero, 1, v0 /* failure */ + hw_ret (p7) + bis zero, zero, zero /* nop */ + bis zero, zero, zero /* nop */ +#endif + +PAL_CALL_DUMMY(EV6__CALL_PAL_0B_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_0C_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_0D_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_0E_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_0F_ENTRY) + +PAL_CALL_DUMMY(EV6__CALL_PAL_10_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_11_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_12_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_13_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_14_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_15_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_16_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_17_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_18_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_19_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_1A_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_1B_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_1C_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_1D_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_1E_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_1F_ENTRY) + +PAL_CALL_DUMMY(EV6__CALL_PAL_20_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_21_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_22_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_23_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_24_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_25_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_26_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_27_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_28_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_29_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_2A_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_2B_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_2C_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_2D_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_2E_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_2F_ENTRY) + +PAL_CALL_DUMMY(EV6__CALL_PAL_30_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_31_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_32_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_33_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_34_ENTRY) + +#if 0 +PAL_CALL_DUMMY(EV6__CALL_PAL_35_ENTRY) +#else + /* swpipl */ +PAL_EXCEPT(SWPIPL, EV6__CALL_PAL_35_ENTRY) + /* Fake the swpipl call just return the maximum ipl + * I'm not going to enable interrupts anyway. + */ + bis zero, 7, v0 + hw_ret/stall(p7) +#endif + +PAL_CALL_DUMMY(EV6__CALL_PAL_36_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_37_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_38_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_39_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_3A_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_3B_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_3C_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_3D_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_3E_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_3F_ENTRY) + +PAL_CALL_DUMMY(EV6__CALL_PAL_80_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_81_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_82_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_83_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_84_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_85_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_86_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_87_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_88_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_89_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_8A_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_8B_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_8C_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_8D_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_8E_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_8F_ENTRY) + +PAL_CALL_DUMMY(EV6__CALL_PAL_90_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_91_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_92_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_93_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_94_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_95_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_96_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_97_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_98_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_99_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_9A_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_9B_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_9C_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_9D_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_9E_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_9F_ENTRY) + +PAL_CALL_DUMMY(EV6__CALL_PAL_A0_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_A1_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_A2_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_A3_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_A4_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_A5_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_A6_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_A7_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_A8_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_A9_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_AA_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_AB_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_AC_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_AD_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_AE_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_AF_ENTRY) + +PAL_CALL_DUMMY(EV6__CALL_PAL_B0_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_B1_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_B2_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_B3_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_B4_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_B5_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_B6_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_B7_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_B8_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_B9_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_BA_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_BB_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_BC_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_BD_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_BE_ENTRY) +PAL_CALL_DUMMY(EV6__CALL_PAL_BF_ENTRY) + +PAL_EXCEPT(dummy, EV6__CALL_PAL_BF_ENTRY + 0x80) + +/* Data for pal_mode_start + * I can't use the magic linker gp magic here so roll my own. + * Note: The linker script ensures that EntryPoint _edata & _end + * are all 8 byte aligned. + */ +EntryPoint_addr: + .quad EntryPoint +_edata_addr: + .quad _edata +_end_addr: + .quad _end +kernel_mode_start_addr: + .quad kernel_mode_start +__fatal_error_non_pal_addr: + .quad __fatal_error_non_pal + +pal_mode_start: + /* relocate to address zero */ + /* The following move routine is not totally + * general. In particular it does not handle + * overlapping memory locations or moving to a higher + * address in memory. + */ + br pv, relocate +relocate: + lda t0,(EntryPoint - relocate)(pv) + ldq_p t1,(EntryPoint_addr - relocate)(pv) + ldq_p t2,(_edata_addr - relocate)(pv) + subq t2, t1, t2 + br Mstart + + /* Move the program */ +Move: ldq_p t3, 0(t0) + subq t2, 8, t2 + addq t0, 8, t0 + stq_p t3, 0(t1) + addq t1, 8, t1 +Mstart: bne t2, Move + + /* set up pal_base register */ + FETCH_BLOCK_ALIGN + ldq_p t0, (EntryPoint_addr - relocate)(pv) + hw_mtpr t0, EV6__PAL_BASE + + /* flush ITB & DTB */ + FETCH_BLOCK_ALIGN + hw_mtpr zero, EV6__ITB_IA + hw_mtpr zero, EV6__DTB_IA + + /* clear i_stat & dc_stat */ + LOAD_CONSTANT32(t0, EV6__I_STAT__W1C) + LOAD_CONSTANT16(t2, EV6__DC_STAT__W1C) + FETCH_BLOCK_ALIGN + hw_mtpr t0, EV6__I_STAT + hw_mtpr t2, EV6__DC_STAT + + /* Initialize I_CTL */ + LOAD_CONSTANT32(t0, EV6__I_CTL__INIT) + FETCH_BLOCK_ALIGN + hw_mtpr t0, EV6__I_CTL + + /* Initialize pctx & m_ctl */ + FETCH_BLOCK_ALIGN + LOAD_CONSTANT16(t0, EV6__PCTX__INIT) + LOAD_CONSTANT16(t2, EV6__M_CTL__INIT) + hw_mtpr t0, EV6__PCTX + hw_mtpr t2, EV6__M_CTL + + /* Initialize ier_cm */ + LOAD_CONSTANT32(t0, EV6__IER__INIT) + hw_mtpr t0, EV6__IER_CM + hw_mtpr zero, EV6__CC + + /* Initialize SIRR */ + bis zero, 1, t0 + sll t0, 32, t0 + hw_mtpr zero, EV6__SIRR + hw_mtpr $1, EV6__CC_CTL + + /* Initialize int_clr */ + LOAD_CONSTANT16(t0, EV6__HW_INT_CLR__INIT) + sll t0, EV6__HW_INT_CLR__MCHK_D__S, t0 + hw_mtpr t0, EV6__HW_INT_CLR + hw_mtpr zero, EV6__DTB_ALT_MODE + + /* set pctr_ctl & va_ctl */ + hw_mtpr zero, EV6__PCTR_CTL + LOAD_CONSTANT16(t0, EV6__VA_CTL__INIT) + hw_mtpr t0, EV6__VA_CTL + FETCH_BLOCK_ALIGN + + /* Clear the asn */ + hw_mtpr zero, EV6__DTB_ASN0 + hw_mtpr zero, EV6__DTB_ASN1 + FETCH_BLOCK_ALIGN + + /* write pctrl_ctl again to clear the 2nd stage overflow flag. + * and force other mtpr to retwir while we are at it. + */ + hw_mtpr zero, EV6__PCTR_CTL | 0xF0 + FETCH_BLOCK_ALIGN + + /* We need to write HW_INT_CLR to avoid a interrup that can occur + * the counters come up in an unpredictable state near overflow. + */ + + lda t0, 3(zero) + sll t0, EV6__HW_INT_CLR__PC__S, t0 + hw_mtpr t0, EV6__HW_INT_CLR + FETCH_BLOCK_ALIGN + hw_mtpr t0, EV6__HW_INT_CLR + FETCH_BLOCK_ALIGN + + /* Clear the fpcr */ + mt_fpcr $f31 + +#if 0 + /* Setup 48 bit address space */ + FETCH_BLOCK_ALIGN + bis zero, 2, t0 + hw_mtpr t0, EV6__VA_CTL + bis zero, 8, t0 + hw_mtpr t0, EV6__M_CTL +#else + /* Setup 40 bit address space */ + FETCH_BLOCK_ALIGN + bis zero, 0, t0 + hw_mtpr t0, EV6__VA_CTL + bis zero, 4, t0 + hw_mtpr t0, EV6__M_CTL +#endif + + FETCH_BLOCK_ALIGN + /* Enable special pal instructions in kernel mode */ + hw_mfpr t0, EV6__I_CTL + lda t1, 1(zero) + sll t1, EV6__I_CTL__HWE__S, t1 + bis t0, t1, t0 + hw_mtpr t0, EV6__I_CTL + + /* Now get out of palmode */ + FETCH_BLOCK_ALIGN + ldq_p pv, (kernel_mode_start_addr - relocate)(pv) + hw_jmp (pv) + +GLOBL(start) + br pv, __start +__start: + /* Some dummy parameters for debugging */ + bis zero, zero, t8 /* CPU speed in picoseconds */ + lda t9, 128*1024*1024 /* Memory size in bytes 128MB */ + bis zero, zero, t11 /* Chip revision */ + + lda a0, (EntryPoint - __start)(pv) + call_pal PAL_swppal + br zero, .-4 /* spin in place */ + + /* __fatal_error_pal Called with: + * p0 - Exception handler that caught the exception + * p7 - Address where the exception occured. + * ra - Potentially valid return address from the code + * that took the exception. + */ + FETCH_BLOCK_ALIGN +__fatal_error_pal: + subq p0, 0x14, a0 + bis p7, p7, a1 + bis ra, ra, a2 + bsr pv, __fatal_error_pal2 +__fatal_error_pal2: + lda pv, (__fatal_error_non_pal - __fatal_error_pal2)(pv) + hw_ret (pv) + diff --git a/src/include/northbridge/alpha/tsunami/core_tsunami.h b/src/include/northbridge/alpha/tsunami/core_tsunami.h new file mode 100644 index 0000000000..d784c5f29b --- /dev/null +++ b/src/include/northbridge/alpha/tsunami/core_tsunami.h @@ -0,0 +1,431 @@ +#ifndef ALPHA_CORE_TSUNAMI_H +#define ALPHA_CORE_TSUNAMI_H + +#include + +/* + * TSUNAMI/TYPHOON are the internal names for the core logic chipset which + * provides memory controller and PCI access for the 21264 based systems. + * + * This file is based on: + * + * Tsunami System Programmers Manual + * Preliminary, Chapters 2-5 + * + */ + +#if USE_48_BIT_KSEG +#define TS_BIAS 0x80000000000UL +#else +#define TS_BIAS 0x10000000000UL +#endif + +/* + * CChip, DChip, and PChip registers + */ + +typedef struct { + volatile unsigned long csr __attribute__((aligned(64))); +} tsunami_64; + +typedef struct { + tsunami_64 csc; + tsunami_64 mtr; + tsunami_64 misc; + tsunami_64 mpd; + tsunami_64 aar0; + tsunami_64 aar1; + tsunami_64 aar2; + tsunami_64 aar3; + tsunami_64 dim0; + tsunami_64 dim1; + tsunami_64 dir0; + tsunami_64 dir1; + tsunami_64 drir; + tsunami_64 prben; + tsunami_64 iic; /* a.k.a. iic0 */ + tsunami_64 wdr; /* a.k.a. iic1 */ + tsunami_64 mpr0; + tsunami_64 mpr1; + tsunami_64 mpr2; + tsunami_64 mpr3; + tsunami_64 mctl; + tsunami_64 __pad1; + tsunami_64 ttr; + tsunami_64 tdr; + tsunami_64 dim2; + tsunami_64 dim3; + tsunami_64 dir2; + tsunami_64 dir3; + tsunami_64 iic2; + tsunami_64 iic3; +} tsunami_cchip; + +typedef struct { + tsunami_64 dsc; + tsunami_64 str; + tsunami_64 drev; +} tsunami_dchip; + +typedef struct { + tsunami_64 wsba[4]; + tsunami_64 wsm[4]; + tsunami_64 tba[4]; + tsunami_64 pctl; + tsunami_64 plat; + tsunami_64 reserved; + tsunami_64 perror; + tsunami_64 perrmask; + tsunami_64 perrset; + tsunami_64 tlbiv; + tsunami_64 tlbia; + tsunami_64 pmonctl; + tsunami_64 pmoncnt; +} tsunami_pchip; + +#define TSUNAMI_cchip ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL)) +#define TSUNAMI_dchip ((tsunami_dchip *)(IDENT_ADDR+TS_BIAS+0x1B0000800UL)) +#define TSUNAMI_pchip0 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x180000000UL)) +#define TSUNAMI_pchip1 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x380000000UL)) +#define TSUNAMI_tig ((volatile unsigned long *) (IDENT_ADDR+TS_BIAS+0x100000000UL)) +extern int TSUNAMI_bootcpu; + +/* + * TSUNAMI Pchip Error register. + */ + +#define perror_m_lost 0x1 +#define perror_m_serr 0x2 +#define perror_m_perr 0x4 +#define perror_m_dcrto 0x8 +#define perror_m_sge 0x10 +#define perror_m_ape 0x20 +#define perror_m_ta 0x40 +#define perror_m_rdpe 0x80 +#define perror_m_nds 0x100 +#define perror_m_rto 0x200 +#define perror_m_uecc 0x400 +#define perror_m_cre 0x800 +#define perror_m_addrl 0xFFFFFFFF0000UL +#define perror_m_addrh 0x7000000000000UL +#define perror_m_cmd 0xF0000000000000UL +#define perror_m_syn 0xFF00000000000000UL +union TPchipPERROR { + struct { + unsigned int perror_v_lost : 1; + unsigned perror_v_serr : 1; + unsigned perror_v_perr : 1; + unsigned perror_v_dcrto : 1; + unsigned perror_v_sge : 1; + unsigned perror_v_ape : 1; + unsigned perror_v_ta : 1; + unsigned perror_v_rdpe : 1; + unsigned perror_v_nds : 1; + unsigned perror_v_rto : 1; + unsigned perror_v_uecc : 1; + unsigned perror_v_cre : 1; + unsigned perror_v_rsvd1 : 4; + unsigned perror_v_addrl : 32; + unsigned perror_v_addrh : 3; + unsigned perror_v_rsvd2 : 1; + unsigned perror_v_cmd : 4; + unsigned perror_v_syn : 8; + } perror_r_bits; + int perror_q_whole [2]; +}; + +/* + * TSUNAMI Pchip Window Space Base Address register. + */ +#define wsba_m_ena 0x1 +#define wsba_m_sg 0x2 +#define wsba_m_ptp 0x4 +#define wsba_m_addr 0xFFF00000 +#define wmask_k_sz1gb 0x3FF00000 +union TPchipWSBA { + struct { + unsigned wsba_v_ena : 1; + unsigned wsba_v_sg : 1; + unsigned wsba_v_ptp : 1; + unsigned wsba_v_rsvd1 : 17; + unsigned wsba_v_addr : 12; + unsigned wsba_v_rsvd2 : 32; + } wsba_r_bits; + int wsba_q_whole [2]; +}; + +/* + * TSUNAMI Pchip Control Register + */ +#define pctl_m_fdsc 0x1 +#define pctl_m_fbtb 0x2 +#define pctl_m_thdis 0x4 +#define pctl_m_chaindis 0x8 +#define pctl_m_tgtlat 0x10 +#define pctl_m_hole 0x20 +#define pctl_m_mwin 0x40 +#define pctl_m_arbena 0x80 +#define pctl_m_prigrp 0x7F00 +#define pctl_m_ppri 0x8000 +#define pctl_m_rsvd1 0x30000 +#define pctl_m_eccen 0x40000 +#define pctl_m_padm 0x80000 +#define pctl_m_cdqmax 0xF00000 +#define pctl_m_rev 0xFF000000 +#define pctl_m_crqmax 0xF00000000UL +#define pctl_m_ptpmax 0xF000000000UL +#define pctl_m_pclkx 0x30000000000UL +#define pctl_m_fdsdis 0x40000000000UL +#define pctl_m_fdwdis 0x80000000000UL +#define pctl_m_ptevrfy 0x100000000000UL +#define pctl_m_rpp 0x200000000000UL +#define pctl_m_pid 0xC00000000000UL +#define pctl_m_rsvd2 0xFFFF000000000000UL + +union TPchipPCTL { + struct { + unsigned pctl_v_fdsc : 1; + unsigned pctl_v_fbtb : 1; + unsigned pctl_v_thdis : 1; + unsigned pctl_v_chaindis : 1; + unsigned pctl_v_tgtlat : 1; + unsigned pctl_v_hole : 1; + unsigned pctl_v_mwin : 1; + unsigned pctl_v_arbena : 1; + unsigned pctl_v_prigrp : 7; + unsigned pctl_v_ppri : 1; + unsigned pctl_v_rsvd1 : 2; + unsigned pctl_v_eccen : 1; + unsigned pctl_v_padm : 1; + unsigned pctl_v_cdqmax : 4; + unsigned pctl_v_rev : 8; + unsigned pctl_v_crqmax : 4; + unsigned pctl_v_ptpmax : 4; + unsigned pctl_v_pclkx : 2; + unsigned pctl_v_fdsdis : 1; + unsigned pctl_v_fdwdis : 1; + unsigned pctl_v_ptevrfy : 1; + unsigned pctl_v_rpp : 1; + unsigned pctl_v_pid : 2; + unsigned pctl_v_rsvd2 : 16; + } pctl_r_bits; + int pctl_q_whole [2]; +}; + +/* + * TSUNAMI Pchip Error Mask Register. + */ +#define perrmask_m_lost 0x1 +#define perrmask_m_serr 0x2 +#define perrmask_m_perr 0x4 +#define perrmask_m_dcrto 0x8 +#define perrmask_m_sge 0x10 +#define perrmask_m_ape 0x20 +#define perrmask_m_ta 0x40 +#define perrmask_m_rdpe 0x80 +#define perrmask_m_nds 0x100 +#define perrmask_m_rto 0x200 +#define perrmask_m_uecc 0x400 +#define perrmask_m_cre 0x800 +#define perrmask_m_rsvd 0xFFFFFFFFFFFFF000UL +union TPchipPERRMASK { + struct { + unsigned int perrmask_v_lost : 1; + unsigned perrmask_v_serr : 1; + unsigned perrmask_v_perr : 1; + unsigned perrmask_v_dcrto : 1; + unsigned perrmask_v_sge : 1; + unsigned perrmask_v_ape : 1; + unsigned perrmask_v_ta : 1; + unsigned perrmask_v_rdpe : 1; + unsigned perrmask_v_nds : 1; + unsigned perrmask_v_rto : 1; + unsigned perrmask_v_uecc : 1; + unsigned perrmask_v_cre : 1; + unsigned perrmask_v_rsvd1 : 20; + unsigned perrmask_v_rsvd2 : 32; + } perrmask_r_bits; + int perrmask_q_whole [2]; +}; + +/* + * Memory spaces: + */ +#define TSUNAMI_HOSE(h) (((unsigned long)(h)) << 33) +#define TSUNAMI_BASE (IDENT_ADDR + TS_BIAS) + +#define TSUNAMI_MEM(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x000000000UL) +#define _TSUNAMI_IACK_SC(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1F8000000UL) +#define TSUNAMI_IO(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FC000000UL) +#define TSUNAMI_CONF(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FE000000UL) + +#define TSUNAMI_IACK_SC _TSUNAMI_IACK_SC(0) /* hack! */ + + +/* + * The canonical non-remaped I/O and MEM addresses have these values + * subtracted out. This is arranged so that folks manipulating ISA + * devices can use their familiar numbers and have them map to bus 0. + */ + +#define TSUNAMI_IO_BIAS TSUNAMI_IO(0) +#define TSUNAMI_MEM_BIAS TSUNAMI_MEM(0) + +/* The IO address space is larger than 0xffff */ +#define TSUNAMI_IO_SPACE (TSUNAMI_CONF(0) - TSUNAMI_IO(0)) + +/* + * Data structure for handling TSUNAMI machine checks: + */ +struct el_TSUNAMI_sysdata_mcheck { +}; + + +/* + * I/O functions: + * + * TSUNAMI, the 21??? PCI/memory support chipset for the EV6 (21264) + * can only use linear accesses to get at PCI memory and I/O spaces. + */ + +#define vucp volatile unsigned char * +#define vusp volatile unsigned short * +#define vuip volatile unsigned int * +#define vulp volatile unsigned long * + +static inline unsigned int tsunami_inb(unsigned long addr) +{ + /* ??? I wish I could get rid of this. But there's no ioremap + equivalent for I/O space. PCI I/O can be forced into the + correct hose's I/O region, but that doesn't take care of + legacy ISA crap. */ + + addr += TSUNAMI_IO_BIAS; + return __kernel_ldbu(*(vucp)addr); +} + +static inline void tsunami_outb(unsigned char b, unsigned long addr) +{ + addr += TSUNAMI_IO_BIAS; + __kernel_stb(b, *(vucp)addr); + mb(); +} + +static inline unsigned int tsunami_inw(unsigned long addr) +{ + addr += TSUNAMI_IO_BIAS; + return __kernel_ldwu(*(vusp)addr); +} + +static inline void tsunami_outw(unsigned short b, unsigned long addr) +{ + addr += TSUNAMI_IO_BIAS; + __kernel_stw(b, *(vusp)addr); + mb(); +} + +static inline unsigned int tsunami_inl(unsigned long addr) +{ + addr += TSUNAMI_IO_BIAS; + return *(vuip)addr; +} + +static inline void tsunami_outl(unsigned int b, unsigned long addr) +{ + addr += TSUNAMI_IO_BIAS; + *(vuip)addr = b; + mb(); +} + +/* + * Memory functions. all accesses are done through linear space. + */ + +static inline unsigned long tsunami_ioremap(unsigned long addr) +{ + return addr + TSUNAMI_MEM_BIAS; +} + +static inline int tsunami_is_ioaddr(unsigned long addr) +{ + return addr >= TSUNAMI_BASE; +} + +static inline unsigned long tsunami_readb(unsigned long addr) +{ + return __kernel_ldbu(*(vucp)addr); +} + +static inline unsigned long tsunami_readw(unsigned long addr) +{ + return __kernel_ldwu(*(vusp)addr); +} + +static inline unsigned long tsunami_readl(unsigned long addr) +{ + return *(vuip)addr; +} + +static inline unsigned long tsunami_readq(unsigned long addr) +{ + return *(vulp)addr; +} + +static inline void tsunami_writeb(unsigned char b, unsigned long addr) +{ + __kernel_stb(b, *(vucp)addr); +} + +static inline void tsunami_writew(unsigned short b, unsigned long addr) +{ + __kernel_stw(b, *(vusp)addr); +} + +static inline void tsunami_writel(unsigned int b, unsigned long addr) +{ + *(vuip)addr = b; +} + +static inline void tsunami_writeq(unsigned long b, unsigned long addr) +{ + *(vulp)addr = b; +} + +/* + * Tig bus functions. + */ + +static inline unsigned long tsunami_tig_readb(unsigned long offset) +{ + return TSUNAMI_tig[offset << (6 - 3)] & 0xff; +} + +static inline void tsunami_tig_writeb(unsigned char b, unsigned long offset) +{ + TSUNAMI_tig[offset << (6 - 3)] = b & 0xff; +} + + +#undef vucp +#undef vusp +#undef vuip +#undef vulp + +#define inb(p) tsunami_inb((unsigned long)(p)) +#define inw(p) tsunami_inw((unsigned long)(p)) +#define inl(p) tsunami_inl((unsigned long)(p)) +#define outb(x,p) tsunami_outb((x),(unsigned long)(p)) +#define outw(x,p) tsunami_outw((x),(unsigned long)(p)) +#define outl(x,p) tsunami_outl((x),(unsigned long)(p)) +#define readb(a) tsunami_readb((unsigned long)(a)) +#define readw(a) tsunami_readw((unsigned long)(a)) +#define readl(a) tsunami_readl((unsigned long)(a)) +#define readq(a) tsunami_readq((unsigned long)(a)) +#define writeb(x,a) tsunami_writeb((x),(unsigned long)(a)) +#define writew(x,a) tsunami_writew((x),(unsigned long)(a)) +#define writel(x,a) tsunami_writel((x),(unsigned long)(a)) +#define writeq(x,a) tsunami_writeq((x),(unsigned long)(a)) +#define ioremap(a) tsunami_ioremap((unsigned long)(a)) +#define is_ioaddr(a) tsunami_is_ioaddr((unsigned long)(a)) + +#endif /* ALPHA_CORE_TSUNAMI_H */ diff --git a/src/mainboard/compaq/ds10/Config b/src/mainboard/compaq/ds10/Config new file mode 100644 index 0000000000..f21433da34 --- /dev/null +++ b/src/mainboard/compaq/ds10/Config @@ -0,0 +1,7 @@ +northbridge alpha/tsunami +southbridge ali/m1543 +#southbridge... +#superio... + + +object mainboard.o diff --git a/src/mainboard/compaq/ds10/mainboard.c b/src/mainboard/compaq/ds10/mainboard.c new file mode 100644 index 0000000000..08b76bfff0 --- /dev/null +++ b/src/mainboard/compaq/ds10/mainboard.c @@ -0,0 +1,6 @@ +#include + +void early_mainboard_init(void) +{ + enable_serial(); +} diff --git a/src/northbridge/acer/m1631/ipl.S b/src/northbridge/acer/m1631/ipl.S index 312de3ec47..58271341a9 100644 --- a/src/northbridge/acer/m1631/ipl.S +++ b/src/northbridge/acer/m1631/ipl.S @@ -189,6 +189,9 @@ nonregistered: sizeram: rorl $16, %ecx /* clear the 'no multi page' bit. */ + /* NOTE: 3/22/01 -- I think this is wrong! -- rgm + * I think we should OR IN 0x1000, which we already did! + */ andw $0xefff, %cx WRITE_MCR0 /* @@ -228,6 +231,10 @@ sizeram: rol $20, %ecx /* set 4 banks. */ orb $1, %cl +/* COMMENT 3-22-01 RGM -- I THINK WE WANT THIS HERE TO TURN + * MULTIBANK ON + andw $0xefff, %cx + */ WRITE_MCR0 /* mov $0x6c, %al @@ -247,6 +254,9 @@ sizeram: movb $7, (%esi) cmpb $0, (%edi) jz 1f /* 4 banks */ + /* NOTE 03-22-01 RGM + * I THINK THIS SHOULD BE 0x180000! + */ orl $0x80000, %ecx /* clear 4 banks */ andb $0xfe, %cl diff --git a/src/southbridge/acer/m1543/Config b/src/southbridge/acer/m1543/Config new file mode 100644 index 0000000000..31fedf9e3f --- /dev/null +++ b/src/southbridge/acer/m1543/Config @@ -0,0 +1,2 @@ +object setup_serial.o + diff --git a/src/southbridge/acer/m1543/setup_serial.c b/src/southbridge/acer/m1543/setup_serial.c new file mode 100644 index 0000000000..77f7a559c4 --- /dev/null +++ b/src/southbridge/acer/m1543/setup_serial.c @@ -0,0 +1,43 @@ +#include +#include + +void enable_serial(void) +{ + const uint16_t config_port = 0x3f0; /* can be 0x370 */ + /* enter configuration mode */ + outb(0x51, config_port); + outb(0x23, config_port); + + /* program logical device 4 */ + outb(0x07, config_port); + outb(0x04, config_port+1); + + /* enable uart1 */ + outb(0x30, config_port); + outb(0x01, config_port+1); + + /* select uart1 I/O base of 0x3f8 */ + outb(0x60, config_port); + outb(0x03, config_port+1); + outb(0x61, config_port); + outb(0xf8, config_port+1); + + /* select uart1 irq 4 */ + outb(0x70, config_port); + outb(0x04, config_port+1); + + /* select uart1 normal (not highspeed) mode */ + outb(0xf0, config_port); + outb(0x00, config_port+1); + + /* select uart1 normal (not IR) mode */ + outb(0xf1, config_port); + outb(0x00, config_port+1); + + /* select uart1 normal (no IR params) */ + outb(0xf2, config_port); + outb(0x00, config_port+1); + + /* exit configuration mode */ + outb(0xbb, config_port); +} diff --git a/util/alpha-common/Config b/util/alpha-common/Config new file mode 100644 index 0000000000..5548869550 --- /dev/null +++ b/util/alpha-common/Config @@ -0,0 +1,9 @@ + +makerule commlib.a: disassm.o romhead.o ; rm -f commlib.a +addaction commlib.a ar cr commlib.a disassm.o romhead.o +addaction commlib.a ar ts commlib.a > /dev/null + + +makerule disassm.o: $(TOP)/util/alpha-common/disassm.c ; $(CC) -g -O -I$(TOP)/util/alpha-common -I$(TOP)/util/alpha-common/include -c $(TOP)/util/alpha-common/disassm.c + +makerule romhead.o: $(TOP)/util/alpha-common/romhead.c ; $(CC) -g -O -I$(TOP)/util/alpha-common -I$(TOP)/util/alpha-common/include -c $(TOP)/util/alpha-common/romhead.c diff --git a/util/alpha-common/Makefile b/util/alpha-common/Makefile new file mode 100644 index 0000000000..4b795c223c --- /dev/null +++ b/util/alpha-common/Makefile @@ -0,0 +1,41 @@ +#Genmake v1.1 01/09/92 Copyright(c) 1990,'91,'92 by Kyle Saunders +CC= cc +CFLAGS= -g -O -I. -I../include +LFLAGS= -lc + +TOUCH = /usr/bin/touch + +# +install: commlib.a + +commlib.a: disassm.o romhead.o + -rm -f commlib.a + ar cr commlib.a disassm.o romhead.o + ar ts commlib.a >/dev/null + +disassm.o: disassm.c + $(CC) $(CFLAGS) -c disassm.c + +romhead.o: romhead.c + $(CC) $(CFLAGS) -c romhead.c + +depend: disassm.c romhead.c + makedepend -f $(MAKEFILE) -- $(CFLAGS) -- disassm.c romhead.c + +clean: + rm -f *.o *~ \#*\# *.bak core + +# DO NOT DELETE THIS LINE -- make depend depends on it. + +disassm.o: /usr/include/stdio.h /usr/include/libio.h /usr/include/_G_config.h +disassm.o: /usr/include/ctype.h /usr/include/features.h +disassm.o: /usr/include/sys/cdefs.h /usr/include/string.h +disassm.o: /usr//include/linux/stddef.h +disassm.o: /usr/include/stdlib.h /usr/include/errno.h +disassm.o: /usr/include/linux/errno.h /usr/include/asm/errno.h +disassm.o: /usr/include/alloca.h +romhead.o: /usr/include/stdlib.h /usr/include/features.h +romhead.o: /usr/include/sys/cdefs.h +romhead.o: /usr/include/errno.h /usr/include/linux/errno.h +romhead.o: /usr/include/asm/errno.h +romhead.o: /usr/include/alloca.h diff --git a/util/alpha-common/c_32_64.c b/util/alpha-common/c_32_64.c new file mode 100644 index 0000000000..4bcaf0823a --- /dev/null +++ b/util/alpha-common/c_32_64.c @@ -0,0 +1,93 @@ +#ifdef CROSS_COMPILE_32_TO_64_BITS + +#include "c_32_64.h" + +int64 zero = {0,0}; + +/* taken from my simulator */ + +/* add an unsigned int32 to a int64 */ +#define add_l_ui(r,l,i) \ + { \ + register unsigned int32 lp, hp, carry; \ + lp = (low32(l) & 0xffff) + ((i) & 0xffff); \ + carry = lp >> 16; \ + hp = (((unsigned)low32(l)) >> 16) + (((unsigned)i) >> 16) + carry;\ + carry = hp >> 16; \ + low32(r) = (hp << 16) | (lp & 0xffff); \ + high32(r) = high32(l) + carry; \ + } + +/* add to int64s */ +#define add_l_l(r,a,b) \ + { \ + register unsigned int32 lp, hp, carry; \ + lp = (low32(a) & 0xffff) + (low32(b) & 0xffff); \ + carry = lp >> 16; \ + hp = (((unsigned)low32(a))>>16) + (((unsigned)low32(b))>>16) + carry;\ + carry = hp >> 16; \ + low32(r) = (hp << 16) | (lp & 0xffff); \ + /* now the hi part */ \ + lp = (high32(a) & 0xffff) + (high32(b) & 0xffff) + carry; \ + carry = lp >> 16; \ + hp = (((unsigned)high32(a))>>16) + (((unsigned)high32(b))>>16) + carry;\ + high32(r) = (hp << 16) | (lp & 0xffff); \ + } + +/* add an int32 to a int64 */ +#define add_l_i(r,l,i) \ + { \ + if (i == 0) { \ + low32(r) = low32(l); high32(r) = high32(l); \ + } else if (i > 0) { \ + add_l_ui(r,l,i); \ + } else { \ + int64 m; \ + low32(m) = i; high32(m) = -1; \ + add_l_l(r,l,m); \ + } \ + } + +/* sub two int64s */ +#define sub_l_l(r,a,b) \ + { \ + register unsigned int32 lp, hp, carry; \ + lp = (low32(a) & 0xffff) + ((~low32(b)) & 0xffff) + 1; \ + carry = lp >> 16; \ + hp = (((unsigned)low32(a))>>16) + ((~(unsigned)low32(b))>>16) + carry;\ + carry = hp >> 16; \ + low32(r) = (hp << 16) | (lp & 0xffff); \ + /* now the hi part */ \ + lp = (high32(a) & 0xffff) + ((~high32(b)) & 0xffff) + carry; \ + carry = lp >> 16; \ + hp = (((unsigned)high32(a))>>16) + ((~(unsigned)high32(b))>>16) + carry;\ + high32(r) = (hp << 16) | (lp & 0xffff); \ + } + +int64 plus(a,b) + int64 a,b; +{ + int64 c; + add_l_l(c,a,b); + return c; +} + +int64 plus_a_32(a,b) + int64 a; + int32 b; +{ + int64 c; + add_l_i(c,a,b); + return c; +} + +int64 minus(a,b) + int64 a,b; +{ + int64 c; + sub_l_l(c,a,b); + return c; +} + +#endif /* CROSS_COMPILE_32_TO_64_BITS */ + diff --git a/util/alpha-common/disassm.c b/util/alpha-common/disassm.c new file mode 100644 index 0000000000..1c211e7996 --- /dev/null +++ b/util/alpha-common/disassm.c @@ -0,0 +1,428 @@ +#ifndef lint +static char *RCSid = "$Id$"; +#endif +/***************************************************************************** + + Copyright © 1993, 1994 Digital Equipment Corporation, + Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, provided +that the copyright notice and this permission notice appear in all copies +of software and supporting documentation, and that the name of Digital not +be used in advertising or publicity pertaining to distribution of the software +without specific, written prior permission. Digital grants this permission +provided that you prominently mark, as not part of the original, any +modifications made to this software or documentation. + +Digital Equipment Corporation disclaims all warranties and/or guarantees +with regard to this software, including all implied warranties of fitness for +a particular purpose and merchantability, and makes no representations +regarding the use of, or the results of the use of, the software and +documentation in terms of correctness, accuracy, reliability, currentness or +otherwise; and you rely on the software, documentation and results solely at +your own risk. + +******************************************************************************/ +/* +** +** FACILITY: +** +** ED64 Software Tools - 21064 Disassembler. +** +** FUNCTIONAL DESCRIPTION: +** +** Common code used by many utilities to disassemble +** 21064 object code. +** +** CALLING ENVIRONMENT: +** +** user mode +** +** AUTHOR: Anthony Berent +** +** CREATION-DATE: NOV-1992 +** +** MODIFIED BY: +** +** +** $Log$ +** Revision 1.1 2001/03/22 21:26:32 rminnich +** testing I HATE CVS +** +** Revision 1.1 2000/03/21 03:56:31 stepan +** Check in current version which is a nearly a 2.2-16 +** + * Revision 4.2 1994/08/06 00:00:00 fdh + * Updated Copyright header + * + * Revision 4.1 1994/07/18 09:42:34 rusling + * Fixed WNT compile warnings. + * +** +** +** AB Nov-1992 First version. +*/ +#include +#include +#include +#include +#include "alpha_op.h" + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +/*==============================*/ +/* Masks for instruction fields */ +/*==============================*/ + +/* Masks used to recognise the instruction */ + +#define OPCODE_MASK 0xFC000000 +#define IMMEDIATE_MASK 0x00001000 +#define JUMP_FUNCTION_MASK 0x0000C000 +#define MEMORY_FUNCTION_MASK 0x0000FFFF +#define INTEGER_OPERATE_FUNCTION_MASK 0x00000FE0 +#define FPOINT_OPERATE_FUNCTION_MASK 0x0000FFE0 +#define HW_MODE_BITS_MASK 0x0000F000 +#define HW_REG_SET_MASK 0x000000E0 + +/* Masks used to find arguments */ +#define RA_MASK 0x03E00000 +#define RB_MASK 0x001F0000 +#define RC_MASK 0x0000001F +#define MEM_DISP_MASK 0x0000FFFF +#define HW_MEM_DISP_MASK 0x00000FFF +#define JUMP_HINT_MASK 0x00003FFF +#define BRANCH_DISP_MASK 0x001FFFFF +#define LITERAL_MASK 0x001FE000 +#define PALCODE_FUNCTION_MASK 0x03FFFFFF +#define INTEGER_OPERATE_SBZ_MASK 0x0000E000 +#define MXPR_DISPLACEMENT_MASK 0x0000000F + +/* Shifts for arguments */ + +#define RA_SHIFT 21 +#define RB_SHIFT 16 +#define RC_SHIFT 0 +#define MEM_DISP_SHIFT 0 +#define HW_MEM_DISP_SHIFT 0 +#define JUMP_HINT_SHIFT 0 +#define BRANCH_DISP_SHIFT 0 +#define LITERAL_SHIFT 13 +#define PALCODE_FUNCTION_SHIFT 0 + + +/* Function to search for a instruction in the opcode table */ +struct alpha_opcode *find_opcode(unsigned int instruction) +{ + struct alpha_opcode *opcodedata = 0; + int i; + + /* Search the opcode table */ + for (i = 0; i < NUMOPCODES; i++) + { + + /* Check if the function code matches */ + if ((alpha_opcodes[i].match & OPCODE_MASK) == + (instruction & OPCODE_MASK)) + { + + /* opcode matches so this is a candidate; check what arguments it + * takes to work out whether */ + /* a function code has to match */ + if (strcmp(alpha_opcodes[i].args, "1,l(2)") == 0 || + strcmp(alpha_opcodes[i].args, "e,l(2)") == 0 || + strcmp(alpha_opcodes[i].args, "1,L") == 0) + { + + /* Memory or branch format without function code */ + opcodedata = &alpha_opcodes[i]; + break; + } + else if (strcmp(alpha_opcodes[i].args, "1,(2),i") == 0) + { + + /* Jump (Memory format branch) format; check the jump function + * mask */ + if ((alpha_opcodes[i].match & JUMP_FUNCTION_MASK) == + (instruction & JUMP_FUNCTION_MASK)) + { + + /* This is what we want */ + opcodedata = &alpha_opcodes[i]; + break; + } + } + else if (strcmp(alpha_opcodes[i].args, "1,t(2)") == 0) + { + + /* EV4 hardware memory access format format; check the mode + * bits */ + if ((alpha_opcodes[i].match & HW_MODE_BITS_MASK) == + (instruction & HW_MODE_BITS_MASK)) + { + + /* This is what we want */ + opcodedata = &alpha_opcodes[i]; + break; + } + } + else if (strcmp(alpha_opcodes[i].args, "R,3") == 0) + { + + /* EV4 internal register access format format; check the + * register set mask */ + if ((alpha_opcodes[i].match & HW_REG_SET_MASK) == + (instruction & HW_REG_SET_MASK)) + { + + /* This is what we want */ + opcodedata = &alpha_opcodes[i]; + break; + } + } + else if (strcmp(alpha_opcodes[i].args, "R,8") == 0) + { + + /* EV4 internal register access format format; check the + * register set mask */ + if ((alpha_opcodes[i].match & HW_REG_SET_MASK) + == (instruction & HW_REG_SET_MASK)) + { + + /* This is what we want */ + opcodedata = &alpha_opcodes[i]; + break; + } + } + else if (strcmp(alpha_opcodes[i].args, "1,2,3") == 0 || + strcmp(alpha_opcodes[i].args, "1,b,3") == 0) + { + + /* Operate format; check immediate bit and function code */ + if ((alpha_opcodes[i].match & IMMEDIATE_MASK) == + (instruction & IMMEDIATE_MASK) && + (alpha_opcodes[i].match & INTEGER_OPERATE_FUNCTION_MASK) == + (instruction & INTEGER_OPERATE_FUNCTION_MASK)) + { + + /* This is what we want */ + opcodedata = &alpha_opcodes[i]; + break; + } + } + else if (strcmp(alpha_opcodes[i].args, "e,f,g") == 0 || + strcmp(alpha_opcodes[i].args, "f,g") == 0) + { + + /* Operate format; check immediate bit and function mask */ + if ((alpha_opcodes[i].match & FPOINT_OPERATE_FUNCTION_MASK) == + (instruction & FPOINT_OPERATE_FUNCTION_MASK)) + { + + /* This is what we want */ + opcodedata = &alpha_opcodes[i]; + break; + } + } + else if (strcmp(alpha_opcodes[i].args, "I") == 0) + { + + /* We have found a PAL code call instruction - there may a more + * precise opcode defined */ + /* so only use this code if we have not already found a match + */ + + if (opcodedata == 0) + opcodedata = &alpha_opcodes[i]; + + /* Don't exit the loop; there may be a more precise match yet */ + } + else if (strcmp(alpha_opcodes[i].args, "0(2)") == 0) + { + + /* Miscellaneous instructions - Memory format with function + * code*/ + if ((alpha_opcodes[i].match & MEMORY_FUNCTION_MASK) == + (instruction & MEMORY_FUNCTION_MASK)) + { + + /* This is what we want */ + opcodedata = &alpha_opcodes[i]; + break; + } + } + else if (strcmp(alpha_opcodes[i].args, "1") == 0) + { + + /* Miscellaneous instructions - Memory format with function + * code but different arguments */ + if ((alpha_opcodes[i].match & MEMORY_FUNCTION_MASK) == + (instruction & MEMORY_FUNCTION_MASK)) + { + + /* This is what we want */ + opcodedata = &alpha_opcodes[i]; + break; + } + } + + else if (strcmp(alpha_opcodes[i].args, "") == 0) + { + + /* Miscellaneous instructions with no arguments; should be + * exact match */ + if (alpha_opcodes[i].match == instruction) + { + + /* This is what we want */ + opcodedata = &alpha_opcodes[i]; + break; + } + } + + /* All other cases are only used for predefined macros and + * psedo-instructions; ignore them */ + } + } + + /* Return the opcode data; it will be null if a match hasn't been found */ + return opcodedata; +} +/* Function to print an instruction and arguments */ +void print_instruction(int instruction, FILE *stream) +{ + struct alpha_opcode *opcodedata; + char *argptr; + int duplicate_reg_bad = FALSE; + int bad_reg_id; + char bad_reg_name; + + + /* Try to find it in the opcode table */ + opcodedata = find_opcode(instruction); + if (opcodedata == 0) + { + fprintf(stream, "\t# BAD INSTRUCTION 0x%08x \n", instruction); + return; + } + + /* Print the instruction name */ + fprintf(stream, "\t%s\t", opcodedata->name); + + /* Now scan its arguments */ + argptr = opcodedata->args; + + while (*argptr != 0) + { + switch (*argptr) + { + + /* Real argument types */ + case '1': + case 'e': + fprintf(stream, "$%i", (instruction & RA_MASK) >> RA_SHIFT); + break; + case '2': + case 'f': + fprintf(stream, "$%i", (instruction & RB_MASK) >> RB_SHIFT); + break; + case '3': + case 'g': + fprintf(stream, "$%i", (instruction & RC_MASK) >> RC_SHIFT); + break; + case 'r': + fprintf(stream, "$%i", (instruction & RA_MASK) >> RA_SHIFT); + if (((instruction & RC_MASK) >> RC_SHIFT) != + ((instruction & RA_MASK) >> RA_SHIFT)) + { + duplicate_reg_bad = TRUE; + bad_reg_name = 'C'; + bad_reg_id = (instruction & RC_MASK) >> RC_SHIFT; + } + break; + case 'R': + fprintf(stream, "$%i", (instruction & RA_MASK) >> RA_SHIFT); + if (((instruction & RB_MASK) >> RB_SHIFT) != + ((instruction & RA_MASK) >> RA_SHIFT)) + { + duplicate_reg_bad = TRUE; + bad_reg_name = 'B'; + bad_reg_id = (instruction & RB_MASK) >> RB_SHIFT; + } + break; + case 'I': + fprintf(stream, "0x%07x", (instruction & + PALCODE_FUNCTION_MASK) >> PALCODE_FUNCTION_SHIFT); + break; + case 'l': + fprintf(stream, "0x%04x", + (instruction & MEM_DISP_MASK) >> MEM_DISP_SHIFT); + break; + case 'h': + fprintf(stream, "0x%04x", + ((instruction & MEM_DISP_MASK) >> MEM_DISP_SHIFT) << 16); + break; + case 't': + + /* Special for EV4 hardware load/store instructions */ + fprintf(stream, "0x%04x", + ((instruction & HW_MEM_DISP_MASK) >> HW_MEM_DISP_SHIFT)); + break; + case 'L': + fprintf(stream, ".+0x%08x", + ((instruction & BRANCH_DISP_MASK) >> BRANCH_DISP_SHIFT) * 4); + break; + case 'i': + fprintf(stream, ".+0x%06x", + ((instruction & JUMP_HINT_MASK) >> JUMP_HINT_SHIFT) * 4); + break; + case 'b': + fprintf(stream, "0x%02x", + (instruction & LITERAL_MASK) >> LITERAL_SHIFT); + break; + case '8': + fprintf(stream, "0x%02x", + (instruction & MXPR_DISPLACEMENT_MASK)); + break; + + /* All other possible characters are punctuation; print what we are + * given */ + default: + fprintf(stream, "%c", *argptr); + } + argptr++; + } + + /* Check for some special cases where fields must be zero etc. */ + if (strcmp(opcodedata->args, "1,2,3") == 0) + { + if ((instruction & INTEGER_OPERATE_SBZ_MASK) != 0) + { + fprintf(stream, " WARNING: SBZ field not zero"); + } + } + else if (strcmp(opcodedata->args, "f,g") == 0) + { + if ((instruction & RA_MASK) != RA_MASK) + { + fprintf(stream, " WARNING: RA field not $31"); + } + } + + if (duplicate_reg_bad) + { + fprintf(stream, + " WARNING: R%c register field does not match RA - value %i", + bad_reg_name, bad_reg_id); + } +} + diff --git a/util/alpha-common/include/Makefile b/util/alpha-common/include/Makefile new file mode 100644 index 0000000000..f65eb925ce --- /dev/null +++ b/util/alpha-common/include/Makefile @@ -0,0 +1,6 @@ +install depend: + +clean: + rm -f *.o *~ \#*\# *.bak *.a core + rcsclean + diff --git a/util/alpha-common/include/a_out.h b/util/alpha-common/include/a_out.h new file mode 100644 index 0000000000..1f24601153 --- /dev/null +++ b/util/alpha-common/include/a_out.h @@ -0,0 +1,218 @@ +/* + * HISTORY + * $Log$ + * Revision 1.1 2001/03/22 21:26:32 rminnich + * testing I HATE CVS + * + * Revision 1.1 2000/03/21 03:56:31 stepan + * Check in current version which is a nearly a 2.2-16 + * + * Revision 4.0 1993/10/18 15:37:42 rusling + * Include file. + * + */ +#ifndef _A_OUT_H_ +#define _A_OUT_H_ 1 +/* This file describes the a.out file format + Copyright (C) 1987 Free Software Foundation, Inc. + +This file is part of GAS, the GNU Assembler. + +GAS is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GAS is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + + /* Alpha's a.out. . . */ + +#ifdef CROSS_COMPILE_32_TO_64_BITS +#include "c_32_64.h" +typedef int32 boolean_t; +#else +#include +#endif + +#if __osf__ +typedef long integer_t; +#endif + + +struct exec { + integer_t a_magic; /* Use macros N_MAGIC, etc for access */ + vm_size_t a_text; /* bytes of text in file */ + vm_size_t a_data; /* bytes of data in file */ + vm_size_t a_bss; /* bytes of auto-zeroed data */ + vm_size_t a_syms; /* bytes of symbol table data in file */ + vm_offset_t a_entry; /* start PC */ + vm_offset_t a_tstart; /* text start, in memory */ + vm_offset_t a_dstart; /* data start, in memory */ + vm_size_t a_trsize; /* bytes of text-relocation info in file */ + vm_size_t a_drsize; /* bytes of data-relocation info in file */ +}; + +#define __LDPGSZ 8192 + +#ifndef OMAGIC +#define OMAGIC 0407 +#define NMAGIC 0410 +#define ZMAGIC 0413 +#endif + +#ifdef CROSS_COMPILE_32_TO_64_BITS + +#define N_BADMAG(x) \ + (((x).a_magic.low)!=OMAGIC && ((x).a_magic.low)!=NMAGIC && ((x).a_magic.low)!=ZMAGIC) +/* Address of the bottom of the text segment. */ +#define N_TXTADDR(x) \ + ((x).a_tstart.low) + +/* Address of the bottom of the data segment. */ +#define N_DATADDR(x) \ + ((x).a_dstart.low) + +/* Text segment offset. */ +#define N_TXTOFF(ex) \ + ((ex).a_magic.low == ZMAGIC ? 0 : sizeof(struct exec)) + +/* Data segment offset. */ +#define N_DATOFF(ex) \ + ((N_TXTOFF(ex)) + ((ex).a_magic.low != ZMAGIC ? (ex).a_text.low : \ + __LDPGSZ + ((ex).a_text.low - 1 & ~(__LDPGSZ - 1)))) + +/* Symbol table offset. */ +#define N_SYMOFF(x) \ + (N_TXTOFF(x) + (x).a_text.low + (x).a_data.low + (x).a_trsize.low + (x).a_drsize.low) + +#define N_STROFF(x) \ + (N_SYMOFF(x) + (x).a_syms.low) + +/* text relocation offset */ +#define N_TRELOFF(x) \ + (N_TXTOFF(x) + (x).a_text.low + (x).a_data.low) + +/* data relocation offset */ +#define N_DRELOFF(x) \ + (N_TXTOFF(x) + (x).a_text.low + (x).a_data.low + (x).a_trsize.low) + +#else + +#define N_BADMAG(x) \ + (((x).a_magic)!=OMAGIC && ((x).a_magic)!=NMAGIC && ((x).a_magic)!=ZMAGIC) + +/* Address of the bottom of the text segment. */ +#define N_TXTADDR(x) \ + ((x).a_tstart) + +/* Address of the bottom of the data segment. */ +#define N_DATADDR(x) \ + ((x).a_dstart) + +/* Text segment offset. */ +#define N_TXTOFF(ex) \ + ((ex).a_magic == ZMAGIC ? 0 : sizeof(struct exec)) + +/* Data segment offset. */ +#define N_DATOFF(ex) \ + ((N_TXTOFF(ex)) + ((ex).a_magic != ZMAGIC ? (ex).a_text : \ + __LDPGSZ + ((ex).a_text - 1 & ~(__LDPGSZ - 1)))) + +/* Symbol table offset. */ +#define N_SYMOFF(x) \ + (N_TXTOFF(x) + (x).a_text + (x).a_data + (x).a_trsize + (x).a_drsize) + +#define N_STROFF(x) \ + (N_SYMOFF(x) + (x).a_syms) + +/* text relocation offset */ +#define N_TRELOFF(x) \ + (N_TXTOFF(x) + (x).a_text + (x).a_data) + +/* data relocation offset */ +#define N_DRELOFF(x) \ + (N_TXTOFF(x) + (x).a_text + (x).a_data + (x).a_trsize) + +#endif + +struct nlist { + union { + char *n_name; + struct nlist *n_next; + long n_strx; + vm_offset_t n_pad_cross_compile; + } n_un; + char n_type; + char n_other; + short n_desc; + int n_pad; + vm_offset_t n_value; +}; + +#define N_UNDF 0x0 +#define N_ABS 0x2 +#define N_TEXT 0x4 +#define N_DATA 0x6 +#define N_BSS 0x8 +#define N_COMM 0x12 +#define N_FN 0x1f +#define N_EXT 0x1 +#define N_TYPE 0x1e +#define N_STAB 0xe0 + +#define N_FORMAT "%016lx" + +enum reloc_type +{ + RELOC_0_7, RELOC_0_15, RELOC_0_31, RELOC_0_63, + RELOC_0_25, RELOC_16_31, RELOC_WDISP21, RELOC_BASE21, + RELOC_WDISP14, RELOC_BASE14, RELOC_32_47, RELOC_48_63, + RELOC_U_16_31, RELOC_U_32_47, RELOC_U_48_63, RELOC_0_12, + RELOC_0_8, + + NO_RELOC, + + BRELOC_0_15, BRELOC_0_31, BRELOC_16_31, + BRSET_0_15, BRSET_16_31 +}; + +struct relocation_info { + vm_offset_t r_address; + unsigned int r_index; + unsigned char r_extern; + enum reloc_type r_type : 8; +#ifdef VMS_HOST + short pad; +#endif + integer_t r_addend; +}; + +/* The following constants are used for actually emitting relocation + * information on Alpha. The relocation_info structure can't be used + * directly because the NT compiler alligns structure members in strange + * ways (it appears to allign all members, including fields, on 4 byte + * boundries.). + */ + +#define R_ADDRESS_OFFSET 0 +#define R_ADDRESS_SIZE 8 +#define R_INDEX_OFFSET 8 +#define R_INDEX_SIZE 4 +#define R_EXTERN_OFFSET 12 +#define R_EXTERN_SIZE 1 +#define R_TYPE_OFFSET 13 +#define R_TYPE_SIZE 1 +#define R_ADDEND_OFFSET 16 +#define R_ADDEND_SIZE 8 +#define RELOCATION_INFO_SIZE 24 + +#endif /* _A_OUT_H_ */ + diff --git a/util/alpha-common/include/alpha_op.h b/util/alpha-common/include/alpha_op.h new file mode 100644 index 0000000000..b9d35f21cb --- /dev/null +++ b/util/alpha-common/include/alpha_op.h @@ -0,0 +1,785 @@ +/* Table of opcodes for the alpha. + Copyright (C) 1989 Free Software Foundation, Inc. + +This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. + +GAS/GDB is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GAS/GDB is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS or GDB; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#if !defined(__STDC__) && !defined(const) +#define const +#endif + +/* + * Structure of an opcode table entry. + */ +struct alpha_opcode +{ + const char *name; + const unsigned int match; /* fixed encoding part of instruction */ + const int isa_float; + const char *args; +}; + +/* + All alpha opcodes are 32 bits, except for the `set' instruction (really + a macro), which is 64 bits. It is handled as a special case. + + The match component is a mask saying which bits must match a + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing one character + for each operand of the instruction. + +Kinds of operands: + 1 ra register + 2 rb register + 3 rc register + r same register for ra and rc + R same register for ra and rb + e fa floating point register. + f fb floating point register. + g fc floating point register. + I 26 bit immediate + l 16 low bits of immediate + h 16 high(er) bits of immediate why ? + L 22 bit PC relative immediate. + i 14 bit PC relative immediate. + b 8 bit literal + G Base-register GET at address, needs macro-expansion + P Base-register PUT at address, needs macro-expansion + Bn builtin macro + t twelve bit displacement + 8 eight bit index + +Syntactic elements + ( + ) base register in "offset(base)" addressing + , separator + +Builtin functions (look like macros to the programmer) + %br the current base register + la %r,A load the (64bit) address in register %r + li %r,N load the constant N in register %r + lo(A) low 16 bits of Address (relocatable) + uml(A) med-low 16 bits, unchanged + umh(A) med-high 16 bits, unchanged + uhi(A) high 16 bits, unchanged + ml(A) med-low, adjusted viz sign of lo(A) + mh(A) med-high, adjusted viz sign of ml(A) + hi(A) high, adjusted viz sign of mh(A) + +*/ + +/* The order of the opcodes in this table is significant: + + * The assembler requires that all instances of the same mnemonic must be + consecutive. If they aren't, the assembler will bomb at runtime. + + * The disassembler should not care about the order of the opcodes. */ + +static struct alpha_opcode alpha_opcodes[] = +{ + +{ "ldgp", 0x00000000, 0, "3,l(1)Ba" }, /* builtin */ +{ "setgp", 0x00000000, 0, "0(1)Bb" }, /* builtin */ + +{ "reml", 0x00000000, 0, "1,2,3B0" }, /* builtin */ +{ "divl", 0x00000000, 0, "1,2,3B1" }, /* builtin */ +{ "remq", 0x00000000, 0, "1,2,3B2" }, /* builtin */ +{ "divq", 0x00000000, 0, "1,2,3B3" }, /* builtin */ +{ "remlu", 0x00000000, 0, "1,2,3B4" }, /* builtin */ +{ "divlu", 0x00000000, 0, "1,2,3B5" }, /* builtin */ +{ "remqu", 0x00000000, 0, "1,2,3B6" }, /* builtin */ +{ "divqu", 0x00000000, 0, "1,2,3B7" }, /* builtin */ + +{ "lda", 0x20000000, 0, "1,l(2)" }, /* 6o+5a+5b+16d */ +{ "lda", 0x20000000, 0, "1,G" }, /* regbase macro */ +{ "ldi", 0x2010FFFF, 0, "1,l"}, /* ldi ra,lit == lda ra,lit(r31) */ +{ "ldah", 0x24000000, 0, "1,l(2)" }, +{ "ldah", 0x24000000, 0, "1,G" }, /* regbase macro */ +{ "lui", 0x2410FFFF, 0, "1,l"}, /* lui ra,lit == ldah ra,lit(r31) */ +{ "ldil", 0x20000000, 0, "1,G" }, /* macro */ +{ "ldiq", 0x20000000, 0, "1,G" }, /* (broken) macro */ + +{ "ldl", 0xa0000000, 0, "1,l(2)" }, +{ "ldl", 0xa0000000, 0, "1,G" }, /* regbase macro */ +{ "ldl_l", 0xa8000000, 0, "1,l(2)" }, +{ "ldl_l", 0xa8000000, 0, "1,G" }, /* regbase macro */ +{ "ldq", 0xa4000000, 0, "1,l(2)" }, +{ "ldq", 0xa4000000, 0, "1,G" }, /* regbase macro */ +{ "ldq_u", 0x2c000000, 0, "1,l(2)" }, +{ "ldq_u", 0x2c000000, 0, "1,G" }, /* regbase macro */ +{ "ldq_l", 0xac000000, 0, "1,l(2)" }, +{ "ldq_l", 0xac000000, 0, "1,G" }, /* regbase macro */ + +{ "stl", 0xb0000000, 0, "1,l(2)" }, +{ "stl", 0xb0000000, 0, "1,P" }, /* regbase macro */ +{ "stl_c", 0xb8000000, 0, "1,l(2)" }, +{ "stl_c", 0xb8000000, 0, "1,P" }, /* regbase macro */ +{ "stq", 0xb4000000, 0, "1,l(2)" }, +{ "stq", 0xb4000000, 0, "1,P" }, /* regbase macro */ +{ "stq_u", 0x3c000000, 0, "1,l(2)" }, +{ "stq_u", 0x3c000000, 0, "1,P" }, /* regbase macro */ +{ "stq_c", 0xbc000000, 0, "1,l(2)" }, +{ "stq_c", 0xbc000000, 0, "1,P" }, /* regbase macro */ + +{ "beq", 0xe4000000, 0, "1,L" }, /* 6o+5a+21d */ +{ "bne", 0xf4000000, 0, "1,L" }, +{ "blt", 0xe8000000, 0, "1,L" }, +{ "ble", 0xec000000, 0, "1,L" }, +{ "bgt", 0xfc000000, 0, "1,L" }, +{ "bge", 0xf8000000, 0, "1,L" }, +{ "blbc", 0xe0000000, 0, "1,L" }, +{ "blbs", 0xf0000000, 0, "1,L" }, + +{ "br", 0xc0000000, 0, "1,L" }, +{ "br", 0xc3e00000, 0, "L" }, /* macro: br zero,disp */ +{ "bsr", 0xd0000000, 0, "1,L" }, +{ "bsr", 0xd3500000, 0, "L" }, /* macro: bsr $ra,L */ + +{ "jmp", 0x68000000, 0, "1,(2),i" }, /* 6o+5a+5b+2A+14d */ +{ "jmp", 0x68000000, 0, "1,(2)" }, +{ "jsr", 0x68004000, 0, "1,(2),i" }, +{ "jsr", 0x68004000, 0, "1,(2)" }, +{ "jsr", 0x68004000, 0, "1,Bc" }, /* macro: lda $pv,L;jsr .. */ + +{ "ret", 0x68008000, 0, "1,(2),i" }, +{ "ret", 0x68008000, 0, "1,(2)" }, +{ "ret", 0x6b5a8000, 0, "" }, /* macro: ret ra,(ra) */ +{ "ret", 0x6be08000, 0, "(2)" }, /* macro: ret zero,(2) */ +{ "ret", 0x681a8000, 0, "1" }, /* macro: ret 1,(ra) */ +{ "jcr", 0x6800c000, 0, "1,(2)" }, +{ "jsr_coroutine", 0x6800c000, 0, "1,(2)" }, + +{ "addl", 0x40000000, 0, "1,2,3" }, /* 6o+5a+5b+4z+7f+5c */ +{ "addl", 0x40001000, 0, "1,b,3" }, /* 6o+5a+8n+1+7f+5c */ +{ "addl/v", 0x40000800, 0, "1,2,3" }, +{ "addl/v", 0x40001800, 0, "1,b,3" }, +{ "s4addl", 0x40000040, 0, "1,2,3" }, +{ "s4addl", 0x40001040, 0, "1,b,3" }, +{ "s8addl", 0x40000240, 0, "1,2,3" }, +{ "s8addl", 0x40001240, 0, "1,b,3" }, +{ "addq", 0x40000400, 0, "1,2,3" }, +{ "addq", 0x40001400, 0, "1,b,3" }, +{ "addq/v", 0x40000c00, 0, "1,2,3" }, + +{ "addq/v", 0x40001c00, 0, "1,b,3" }, +{ "s4addq", 0x40000440, 0, "1,2,3" }, +{ "s4addq", 0x40001440, 0, "1,b,3" }, +{ "s8addq", 0x40000640, 0, "1,2,3" }, +{ "s8addq", 0x40001640, 0, "1,b,3" }, +{ "cmpeq", 0x400005a0, 0, "1,2,3" }, +{ "cmpeq", 0x400015a0, 0, "1,b,3" }, +{ "cmplt", 0x400009a0, 0, "1,2,3" }, +{ "cmplt", 0x400019a0, 0, "1,b,3" }, +{ "cmple", 0x40000da0, 0, "1,2,3" }, +{ "cmple", 0x40001da0, 0, "1,b,3" }, +{ "cmpult", 0x400003a0, 0, "1,2,3" }, +{ "cmpult", 0x400013a0, 0, "1,b,3" }, +{ "cmpule", 0x400007a0, 0, "1,2,3" }, +{ "cmpule", 0x400017a0, 0, "1,b,3" }, +{ "subl", 0x40000120, 0, "1,2,3" }, +{ "subl", 0x40001120, 0, "1,b,3" }, +{ "subl/v", 0x40000920, 0, "1,2,3" }, +{ "subl/v", 0x40001920, 0, "1,b,3" }, +{ "s4subl", 0x40000160, 0, "1,2,3" }, +{ "s4subl", 0x40001160, 0, "1,b,3" }, +{ "s8subl", 0x40000360, 0, "1,2,3" }, +{ "s8subl", 0x40001360, 0, "1,b,3" }, +{ "subq", 0x40000520, 0, "1,2,3" }, +{ "subq", 0x40001520, 0, "1,b,3" }, +{ "subq/v", 0x40000d20, 0, "1,2,3" }, +{ "subq/v", 0x40001d20, 0, "1,b,3" }, +{ "s4subq", 0x40000560, 0, "1,2,3" }, +{ "s4subq", 0x40001560, 0, "1,b,3" }, +{ "s8subq", 0x40000760, 0, "1,2,3" }, +{ "s8subq", 0x40001760, 0, "1,b,3" }, +{ "cmpbge", 0x400001e0, 0, "1,2,3" }, +{ "cmpbge", 0x400011e0, 0, "1,b,3" }, + +{ "mull", 0x4c000000, 0, "1,2,3" }, +{ "mull", 0x4c001000, 0, "1,b,3" }, +{ "mull/v", 0x4c000800, 0, "1,2,3" }, +{ "mull/v", 0x4c001800, 0, "1,b,3" }, +{ "mulq", 0x4c000400, 0, "1,2,3" }, +{ "mulq", 0x4c001400, 0, "1,b,3" }, +{ "mulq/v", 0x4c000c00, 0, "1,2,3" }, +{ "mulq/v", 0x4c001c00, 0, "1,b,3" }, +{ "umulh", 0x4c000600, 0, "1,2,3" }, +{ "umulh", 0x4c001600, 0, "1,b,3" }, + +{ "clr", 0x47ff0400, 0, "3" }, /* macro: or zero,zero,rc */ +{ "negl", 0x43e00120, 0, "2,3" }, /* macro: subl zero,rb,rc */ +{ "negl_v", 0x43e00920, 0, "2,3" }, /* macro: subl_v zero,rb,rc */ +{ "negq", 0x43e00520, 0, "2,3" }, /* macro: subq zero,rb,rc */ +{ "negq_v", 0x43e00d20, 0, "2,3" }, /* macro: subq_v zero,rb,rc */ +{ "sextl", 0x43e00000, 0, "2,3" }, /* macro: addl zero,rb,rc */ + +{ "and", 0x44000000, 0, "1,2,3" }, +{ "and", 0x44001000, 0, "1,b,3" }, +{ "and", 0x44000000, 0, "r,2" }, /* macro: and ra,rb,ra */ +{ "and", 0x44001000, 0, "r,b" }, /* macro: and ra,#,ra */ +{ "or", 0x44000400, 0, "1,2,3" }, +{ "or", 0x44001400, 0, "1,b,3" }, +{ "or", 0x44000400, 0, "r,2" }, /* macro: or ra,rb,ra */ +{ "or", 0x44001400, 0, "r,b" }, /* macro: or ra,#,ra */ +{ "bis", 0x44000400, 0, "1,2,3" }, +{ "bis", 0x44001400, 0, "1,b,3" }, +{ "bis", 0x44000400, 0, "r,2" }, /* macro: or ra,rb,ra */ +{ "bis", 0x44001400, 0, "r,b" }, /* macro: or ra,#,ra */ +{ "movi", 0x47E01400, 0, "b,3"}, /* movi lit,rc == bis r31,lit,rc */ +{ "xor", 0x44000800, 0, "1,2,3" }, +{ "xor", 0x44001800, 0, "1,b,3" }, +{ "xor", 0x44000800, 0, "r,2" }, /* macro: ra,rb,ra */ +{ "xor", 0x44001800, 0, "r,b" }, /* macro: ra,#,ra */ +{ "andnot", 0x44000100, 0, "1,2,3" }, +{ "andnot", 0x44001100, 0, "1,b,3" }, +{ "andnot", 0x44000100, 0, "r,2" }, /* macro: ra,#,ra */ +{ "andnot", 0x44001100, 0, "r,b" }, /* macro: ra,#,ra */ +{ "bic", 0x44000100, 0, "1,2,3" }, +{ "bic", 0x44001100, 0, "1,b,3" }, +{ "bic", 0x44000100, 0, "r,2" }, /* macro: ra,#,ra */ +{ "bic", 0x44001100, 0, "r,b" }, /* macro: ra,#,ra */ +{ "ornot", 0x44000500, 0, "1,2,3" }, +{ "ornot", 0x44001500, 0, "1,b,3" }, +{ "ornot", 0x44000500, 0, "r,2" }, /* macro: ra,#,ra */ +{ "ornot", 0x44001500, 0, "r,b" }, /* macro: ra,#,ra */ +{ "not", 0x47e00500, 0, "2,3" }, /* macro: ornot zero,.. */ +{ "not", 0x47e01500, 0, "b,3" }, +{ "xornot", 0x44000900, 0, "1,2,3" }, +{ "xornot", 0x44001900, 0, "1,b,3" }, +{ "xornot", 0x44000900, 0, "r,2" }, /* macro: ra,#,ra */ +{ "xornot", 0x44001900, 0, "r,b" }, /* macro: ra,#,ra */ +{ "eqv", 0x44000900, 0, "1,2,3" }, +{ "eqv", 0x44001900, 0, "1,b,3" }, +{ "eqv", 0x44000900, 0, "r,2" }, /* macro: ra,#,ra */ +{ "eqv", 0x44001900, 0, "r,b" }, /* macro: ra,#,ra */ + +{ "cmoveq", 0x44000480, 0, "1,2,3" }, +{ "cmoveq", 0x44001480, 0, "1,b,3" }, +{ "cmovne", 0x440004c0, 0, "1,2,3" }, +{ "cmovne", 0x440014c0, 0, "1,b,3" }, +{ "cmovlt", 0x44000880, 0, "1,2,3" }, +{ "cmovlt", 0x44001880, 0, "1,b,3" }, +{ "cmovle", 0x44000c80, 0, "1,2,3" }, +{ "cmovle", 0x44001c80, 0, "1,b,3" }, +{ "cmovgt", 0x44000cc0, 0, "1,2,3" }, +{ "cmovgt", 0x44001cc0, 0, "1,b,3" }, +{ "cmovge", 0x440008c0, 0, "1,2,3" }, +{ "cmovge", 0x440018c0, 0, "1,b,3" }, +{ "cmovlbc", 0x440002c0, 0, "1,2,3" }, +{ "cmovlbc", 0x440012c0, 0, "1,b,3" }, +{ "cmovlbs", 0x44000280, 0, "1,2,3" }, +{ "cmovlbs", 0x44001280, 0, "1,b,3" }, + +{ "sll", 0x48000720, 0, "1,2,3" }, +{ "sll", 0x48001720, 0, "1,b,3" }, +{ "srl", 0x48000680, 0, "1,2,3" }, +{ "srl", 0x48001680, 0, "1,b,3" }, +{ "sra", 0x48000780, 0, "1,2,3" }, +{ "sra", 0x48001780, 0, "1,b,3" }, + +{ "extbl", 0x480000c0, 0, "1,2,3" }, +{ "extbl", 0x480010c0, 0, "1,b,3" }, +{ "extwl", 0x480002c0, 0, "1,2,3" }, +{ "extwl", 0x480012c0, 0, "1,b,3" }, +{ "extll", 0x480004c0, 0, "1,2,3" }, +{ "extll", 0x480014c0, 0, "1,b,3" }, +{ "extql", 0x480006c0, 0, "1,2,3" }, +{ "extql", 0x480016c0, 0, "1,b,3" }, +{ "extwh", 0x48000b40, 0, "1,2,3" }, +{ "extwh", 0x48001b40, 0, "1,b,3" }, +{ "extlh", 0x48000d40, 0, "1,2,3" }, +{ "extlh", 0x48001d40, 0, "1,b,3" }, +{ "extqh", 0x48000f40, 0, "1,2,3" }, +{ "extqh", 0x48001f40, 0, "1,b,3" }, +{ "insbl", 0x48000160, 0, "1,2,3" }, +{ "insbl", 0x48001160, 0, "1,b,3" }, +{ "inswl", 0x48000360, 0, "1,2,3" }, +{ "inswl", 0x48001360, 0, "1,b,3" }, +{ "insll", 0x48000560, 0, "1,2,3" }, +{ "insll", 0x48001560, 0, "1,b,3" }, +{ "insql", 0x48000760, 0, "1,2,3" }, +{ "insql", 0x48001760, 0, "1,b,3" }, +{ "inswh", 0x48000ae0, 0, "1,2,3" }, +{ "inswh", 0x48001ae0, 0, "1,b,3" }, +{ "inslh", 0x48000ce0, 0, "1,2,3" }, +{ "inslh", 0x48001ce0, 0, "1,b,3" }, +{ "insqh", 0x48000ee0, 0, "1,2,3" }, +{ "insqh", 0x48001ee0, 0, "1,b,3" }, +{ "mskbl", 0x48000040, 0, "1,2,3" }, +{ "mskbl", 0x48001040, 0, "1,b,3" }, +{ "mskwl", 0x48000240, 0, "1,2,3" }, +{ "mskwl", 0x48001240, 0, "1,b,3" }, +{ "mskll", 0x48000440, 0, "1,2,3" }, +{ "mskll", 0x48001440, 0, "1,b,3" }, +{ "mskql", 0x48000640, 0, "1,2,3" }, +{ "mskql", 0x48001640, 0, "1,b,3" }, +{ "mskwh", 0x48000a40, 0, "1,2,3" }, +{ "mskwh", 0x48001a40, 0, "1,b,3" }, +{ "msklh", 0x48000c40, 0, "1,2,3" }, +{ "msklh", 0x48001c40, 0, "1,b,3" }, +{ "mskqh", 0x48000e40, 0, "1,2,3" }, +{ "mskqh", 0x48001e40, 0, "1,b,3" }, +{ "zap", 0x48000600, 0, "1,2,3" }, +{ "zap", 0x48001600, 0, "1,b,3" }, +{ "zapnot", 0x48000620, 0, "1,2,3" }, +{ "zapnot", 0x48001620, 0, "1,b,3" }, + +/* + * Floating point instructions + */ +{ "ldf", 0x80000000, 1, "e,l(2)" }, /* 6o+5a+5b+16d */ +{ "ldf", 0x80000000, 1, "e,G" }, /* regbase macro */ +{ "ldg", 0x84000000, 1, "e,l(2)" }, +{ "ldg", 0x84000000, 1, "e,G" }, /* regbase macro */ +{ "lds", 0x88000000, 1, "e,l(2)" }, +{ "lds", 0x88000000, 1, "e,G" }, /* regbase macro */ +{ "ldt", 0x8c000000, 1, "e,l(2)" }, +{ "ldt", 0x8c000000, 1, "e,G" }, /* regbase macro */ +{ "stf", 0x90000000, 1, "e,l(2)" }, +{ "stf", 0x90000000, 1, "e,P" }, /* regbase macro */ +{ "stg", 0x94000000, 1, "e,l(2)" }, +{ "stg", 0x94000000, 1, "e,P" }, /* regbase macro */ +{ "sts", 0x98000000, 1, "e,l(2)" }, +{ "sts", 0x98000000, 1, "e,P" }, /* regbase macro */ +{ "stt", 0x9c000000, 1, "e,l(2)" }, +{ "stt", 0x9c000000, 1, "e,P" }, /* regbase macro */ + +{ "fbeq", 0xc4000000, 1, "e,L" }, /* 6o+5a+21d */ +{ "fbne", 0xd4000000, 1, "e,L" }, +{ "fblt", 0xc8000000, 1, "e,L" }, +{ "fble", 0xcc000000, 1, "e,L" }, +{ "fbgt", 0xdc000000, 1, "e,L" }, +{ "fbge", 0xd8000000, 1, "e,L" }, + +/* All subsets (opcode 0x17) */ +{ "cpys", 0x5c000400, 1, "e,f,g" }, /* 6o+5a+5b+11f+5c */ +{ "cpysn", 0x5c000420, 1, "e,f,g" }, +{ "cpyse", 0x5c000440, 1, "e,f,g" }, + +{ "cvtlq", 0x5fe00200, 1, "f,g" }, +{ "cvtql", 0x5fe00600, 1, "f,g" }, +{ "cvtql/v", 0x5fe02600, 1, "f,g" }, +{ "cvtql/sv", 0x5fe06600, 1, "f,g" }, + +{ "fcmoveq", 0x5c000540, 1, "e,f,g" }, +{ "fcmovne", 0x5c000560, 1, "e,f,g" }, +{ "fcmovlt", 0x5c000580, 1, "e,f,g" }, +{ "fcmovle", 0x5c0005c0, 1, "e,f,g" }, +{ "fcmovgt", 0x5c0005e0, 1, "e,f,g" }, +{ "fcmovge", 0x5c0005a0, 1, "e,f,g" }, + +{ "mf_fpcr", 0x5c0004a0, 1, "E" }, +{ "mt_fpcr", 0x5c000480, 1, "E" }, + +/* Vax subset (opcode 0x15) */ +{ "addf", 0x54001000, 1, "e,f,g" }, +{ "addf/c", 0x54000000, 1, "e,f,g" }, +{ "addf/u", 0x54003000, 1, "e,f,g" }, +{ "addf/uc", 0x54002000, 1, "e,f,g" }, +{ "addf/s", 0x54009000, 1, "e,f,g" }, +{ "addf/sc", 0x54008000, 1, "e,f,g" }, +{ "addf/su", 0x5400b000, 1, "e,f,g" }, +{ "addf/suc", 0x5400a000, 1, "e,f,g" }, +{ "addg", 0x54001400, 1, "e,f,g" }, +{ "addg/c", 0x54000400, 1, "e,f,g" }, +{ "addg/u", 0x54003400, 1, "e,f,g" }, +{ "addg/uc", 0x54002400, 1, "e,f,g" }, +{ "addg/s", 0x54009400, 1, "e,f,g" }, +{ "addg/sc", 0x54008400, 1, "e,f,g" }, +{ "addg/su", 0x5400b400, 1, "e,f,g" }, +{ "addg/suc", 0x5400a400, 1, "e,f,g" }, +{ "subf", 0x54001020, 1, "e,f,g" }, +{ "subf/c", 0x54000020, 1, "e,f,g" }, +{ "subf/u", 0x54003020, 1, "e,f,g" }, +{ "subf/uc", 0x54002020, 1, "e,f,g" }, +{ "subf/s", 0x54009020, 1, "e,f,g" }, +{ "subf/sc", 0x54008020, 1, "e,f,g" }, +{ "subf/su", 0x5400b020, 1, "e,f,g" }, +{ "subf/suc", 0x5400a020, 1, "e,f,g" }, +{ "subg", 0x54001420, 1, "e,f,g" }, +{ "subg/c", 0x54000420, 1, "e,f,g" }, +{ "subg/u", 0x54003420, 1, "e,f,g" }, +{ "subg/uc", 0x54002420, 1, "e,f,g" }, +{ "subg/s", 0x54009420, 1, "e,f,g" }, +{ "subg/sc", 0x54008420, 1, "e,f,g" }, +{ "subg/su", 0x5400b420, 1, "e,f,g" }, +{ "subg/suc", 0x5400a420, 1, "e,f,g" }, + +{ "cmpgeq", 0x540014a0, 1, "e,f,g" }, +{ "cmpgeq/s", 0x540094a0, 1, "e,f,g" }, +{ "cmpglt", 0x540014c0, 1, "e,f,g" }, +{ "cmpglt/s", 0x540094c0, 1, "e,f,g" }, +{ "cmpgle", 0x540014e0, 1, "e,f,g" }, +{ "cmpgle/s", 0x540094e0, 1, "e,f,g" }, + +{ "cvtgq", 0x57e015e0, 1, "f,g" }, +{ "cvtgq/c", 0x57e005e0, 1, "f,g" }, +{ "cvtgq/v", 0x57e035e0, 1, "f,g" }, +{ "cvtgq/vc", 0x57e025e0, 1, "f,g" }, +{ "cvtgq/s", 0x57e095e0, 1, "f,g" }, +{ "cvtgq/sc", 0x57e085e0, 1, "f,g" }, +{ "cvtgq/sv", 0x57e0b5e0, 1, "f,g" }, +{ "cvtgq/svc", 0x57e0a5e0, 1, "f,g" }, +{ "cvtqf", 0x57e01780, 1, "f,g" }, +{ "cvtqf/c", 0x57e00780, 1, "f,g" }, +{ "cvtqf/s", 0x57e09780, 1, "f,g" }, +{ "cvtqf/sc", 0x57e08780, 1, "f,g" }, +{ "cvtqg", 0x57e017c0, 1, "f,g" }, +{ "cvtqg/c", 0x57e007c0, 1, "f,g" }, +{ "cvtqg/s", 0x57e097c0, 1, "f,g" }, +{ "cvtqg/sc", 0x57e087c0, 1, "f,g" }, +{ "cvtdg", 0x57e013c0, 1, "f,g" }, +{ "cvtdg/c", 0x57e003c0, 1, "f,g" }, +{ "cvtdg/u", 0x57e033c0, 1, "f,g" }, +{ "cvtdg/uc", 0x57e023c0, 1, "f,g" }, +{ "cvtdg/s", 0x57e093c0, 1, "f,g" }, +{ "cvtdg/sc", 0x57e083c0, 1, "f,g" }, +{ "cvtdg/su", 0x57e0b3c0, 1, "f,g" }, +{ "cvtdg/suc", 0x57e0a3c0, 1, "f,g" }, +{ "cvtgd", 0x57e015a0, 1, "f,g" }, +{ "cvtgd/c", 0x57e005a0, 1, "f,g" }, +{ "cvtgd/u", 0x57e035a0, 1, "f,g" }, +{ "cvtgd/uc", 0x57e025a0, 1, "f,g" }, +{ "cvtgd/s", 0x57e095a0, 1, "f,g" }, +{ "cvtgd/sc", 0x57e085a0, 1, "f,g" }, +{ "cvtgd/su", 0x57e0b5a0, 1, "f,g" }, +{ "cvtgd/suc", 0x57e0a5a0, 1, "f,g" }, +{ "cvtgf", 0x57e01580, 1, "f,g" }, +{ "cvtgf/c", 0x57e00580, 1, "f,g" }, +{ "cvtgf/u", 0x57e03580, 1, "f,g" }, +{ "cvtgf/uc", 0x57e02580, 1, "f,g" }, +{ "cvtgf/s", 0x57e09580, 1, "f,g" }, +{ "cvtgf/sc", 0x57e08580, 1, "f,g" }, +{ "cvtgf/su", 0x57e0b580, 1, "f,g" }, +{ "cvtgf/suc", 0x57e0a580, 1, "f,g" }, + +{ "divf", 0x54001060, 1, "e,f,g" }, +{ "divf/c", 0x54000060, 1, "e,f,g" }, +{ "divf/u", 0x54003060, 1, "e,f,g" }, +{ "divf/uc", 0x54002060, 1, "e,f,g" }, +{ "divf/s", 0x54009060, 1, "e,f,g" }, +{ "divf/sc", 0x54008060, 1, "e,f,g" }, +{ "divf/su", 0x5400b060, 1, "e,f,g" }, +{ "divf/suc", 0x5400a060, 1, "e,f,g" }, +{ "divg", 0x54001460, 1, "e,f,g" }, +{ "divg/c", 0x54000460, 1, "e,f,g" }, +{ "divg/u", 0x54003460, 1, "e,f,g" }, +{ "divg/uc", 0x54002460, 1, "e,f,g" }, +{ "divg/s", 0x54009460, 1, "e,f,g" }, +{ "divg/sc", 0x54008460, 1, "e,f,g" }, +{ "divg/su", 0x5400b460, 1, "e,f,g" }, +{ "divg/suc", 0x5400a460, 1, "e,f,g" }, +{ "mulf", 0x54001040, 1, "e,f,g" }, +{ "mulf/c", 0x54000040, 1, "e,f,g" }, +{ "mulf/u", 0x54003040, 1, "e,f,g" }, +{ "mulf/uc", 0x54002040, 1, "e,f,g" }, +{ "mulf/s", 0x54009040, 1, "e,f,g" }, +{ "mulf/sc", 0x54008040, 1, "e,f,g" }, +{ "mulf/su", 0x5400b040, 1, "e,f,g" }, +{ "mulf/suc", 0x5400a040, 1, "e,f,g" }, +{ "mulg", 0x54001440, 1, "e,f,g" }, +{ "mulg/c", 0x54000440, 1, "e,f,g" }, +{ "mulg/u", 0x54003440, 1, "e,f,g" }, +{ "mulg/uc", 0x54002440, 1, "e,f,g" }, +{ "mulg/s", 0x54009440, 1, "e,f,g" }, +{ "mulg/sc", 0x54008440, 1, "e,f,g" }, +{ "mulg/su", 0x5400b440, 1, "e,f,g" }, +{ "mulg/suc", 0x5400a440, 1, "e,f,g" }, + +/* IEEE subset (opcode 0x16) */ +{ "adds", 0x58001000, 1, "e,f,g" }, +{ "adds/c", 0x58000000, 1, "e,f,g" }, +{ "adds/m", 0x58000800, 1, "e,f,g" }, +{ "adds/d", 0x58001800, 1, "e,f,g" }, +{ "adds/u", 0x58003000, 1, "e,f,g" }, +{ "adds/uc", 0x58002000, 1, "e,f,g" }, +{ "adds/um", 0x58002800, 1, "e,f,g" }, +{ "adds/ud", 0x58003800, 1, "e,f,g" }, +{ "adds/su", 0x5800b000, 1, "e,f,g" }, +{ "adds/suc", 0x5800a000, 1, "e,f,g" }, +{ "adds/sum", 0x5800a800, 1, "e,f,g" }, +{ "adds/sud", 0x5800b800, 1, "e,f,g" }, +{ "adds/sui", 0x5800f000, 1, "e,f,g" }, +{ "adds/suic", 0x5800e000, 1, "e,f,g" }, +{ "adds/suim", 0x5800e800, 1, "e,f,g" }, +{ "adds/suid", 0x5800f800, 1, "e,f,g" }, +{ "addt", 0x58001400, 1, "e,f,g" }, +{ "addt/c", 0x58000400, 1, "e,f,g" }, +{ "addt/m", 0x58000c00, 1, "e,f,g" }, +{ "addt/d", 0x58001c00, 1, "e,f,g" }, +{ "addt/u", 0x58003400, 1, "e,f,g" }, +{ "addt/uc", 0x58002400, 1, "e,f,g" }, +{ "addt/um", 0x58002c00, 1, "e,f,g" }, +{ "addt/ud", 0x58003c00, 1, "e,f,g" }, +{ "addt/su", 0x5800b400, 1, "e,f,g" }, +{ "addt/suc", 0x5800a400, 1, "e,f,g" }, +{ "addt/sum", 0x5800ac00, 1, "e,f,g" }, +{ "addt/sud", 0x5800bc00, 1, "e,f,g" }, +{ "addt/sui", 0x5800f400, 1, "e,f,g" }, +{ "addt/suic", 0x5800e400, 1, "e,f,g" }, +{ "addt/suim", 0x5800ec00, 1, "e,f,g" }, +{ "addt/suid", 0x5800fc00, 1, "e,f,g" }, +{ "subs", 0x58001020, 1, "e,f,g" }, +{ "subs/c", 0x58000020, 1, "e,f,g" }, +{ "subs/m", 0x58000820, 1, "e,f,g" }, +{ "subs/d", 0x58001820, 1, "e,f,g" }, +{ "subs/u", 0x58003020, 1, "e,f,g" }, +{ "subs/uc", 0x58002020, 1, "e,f,g" }, +{ "subs/um", 0x58002820, 1, "e,f,g" }, +{ "subs/ud", 0x58003820, 1, "e,f,g" }, +{ "subs/su", 0x5800b020, 1, "e,f,g" }, +{ "subs/suc", 0x5800a020, 1, "e,f,g" }, +{ "subs/sum", 0x5800a820, 1, "e,f,g" }, +{ "subs/sud", 0x5800b820, 1, "e,f,g" }, +{ "subs/sui", 0x5800f020, 1, "e,f,g" }, +{ "subs/suic", 0x5800e020, 1, "e,f,g" }, +{ "subs/suim", 0x5800e820, 1, "e,f,g" }, +{ "subs/suid", 0x5800f820, 1, "e,f,g" }, +{ "subt", 0x58001420, 1, "e,f,g" }, +{ "subt/c", 0x58000420, 1, "e,f,g" }, +{ "subt/m", 0x58000c20, 1, "e,f,g" }, +{ "subt/d", 0x58001c20, 1, "e,f,g" }, +{ "subt/u", 0x58003420, 1, "e,f,g" }, +{ "subt/uc", 0x58002420, 1, "e,f,g" }, +{ "subt/um", 0x58002c20, 1, "e,f,g" }, +{ "subt/ud", 0x58003c20, 1, "e,f,g" }, +{ "subt/su", 0x5800b420, 1, "e,f,g" }, +{ "subt/suc", 0x5800a420, 1, "e,f,g" }, +{ "subt/sum", 0x5800ac20, 1, "e,f,g" }, +{ "subt/sud", 0x5800bc20, 1, "e,f,g" }, +{ "subt/sui", 0x5800f420, 1, "e,f,g" }, +{ "subt/suic", 0x5800e420, 1, "e,f,g" }, +{ "subt/suim", 0x5800ec20, 1, "e,f,g" }, +{ "subt/suid", 0x5800fc20, 1, "e,f,g" }, + +{ "cmpteq", 0x580014a0, 1, "e,f,g" }, +{ "cmpteq/su", 0x5800b4a0, 1, "e,f,g" }, +{ "cmptlt", 0x580014c0, 1, "e,f,g" }, +{ "cmptlt/su", 0x5800b4c0, 1, "e,f,g" }, +{ "cmptle", 0x580014e0, 1, "e,f,g" }, +{ "cmptle/su", 0x5800b4e0, 1, "e,f,g" }, +{ "cmptun", 0x58001480, 1, "e,f,g" }, +{ "cmptun/su", 0x5800b480, 1, "e,f,g" }, + +{ "cvttq", 0x5be015e0, 1, "f,g" }, +{ "cvttq/c", 0x5be005e0, 1, "f,g" }, +{ "cvttq/v", 0x5be035e0, 1, "f,g" }, +{ "cvttq/vc", 0x5be025e0, 1, "f,g" }, +{ "cvttq/sv", 0x5be0b5e0, 1, "f,g" }, +{ "cvttq/svc", 0x5be0a5e0, 1, "f,g" }, +{ "cvttq/svi", 0x5be0f5e0, 1, "f,g" }, +{ "cvttq/svic", 0x5be0e5e0, 1, "f,g" }, +{ "cvtqs", 0x5be01780, 1, "f,g" }, +{ "cvtqs/c", 0x5be00780, 1, "f,g" }, +{ "cvtqs/m", 0x5be00f80, 1, "f,g" }, +{ "cvtqs/d", 0x5be01f80, 1, "f,g" }, +{ "cvtqs/sui", 0x5be0f780, 1, "f,g" }, +{ "cvtqs/suic", 0x5be0e780, 1, "f,g" }, +{ "cvtqs/suim", 0x5be0ef80, 1, "f,g" }, +{ "cvtqs/suid", 0x5be0ff80, 1, "f,g" }, +{ "cvtqt", 0x5be017c0, 1, "f,g" }, +{ "cvtqt/c", 0x5be007c0, 1, "f,g" }, +{ "cvtqt/m", 0x5be00fc0, 1, "f,g" }, +{ "cvtqt/d", 0x5be01fc0, 1, "f,g" }, +{ "cvtqt/sui", 0x5be0f7c0, 1, "f,g" }, +{ "cvtqt/suic", 0x5be0e7c0, 1, "f,g" }, +{ "cvtqt/suim", 0x5be0efc0, 1, "f,g" }, +{ "cvtqt/suid", 0x5be0ffc0, 1, "f,g" }, +{ "cvtts", 0x5be01580, 1, "f,g" }, +{ "cvtts/c", 0x5be00580, 1, "f,g" }, +{ "cvtts/m", 0x5be00d80, 1, "f,g" }, +{ "cvtts/d", 0x5be01d80, 1, "f,g" }, +{ "cvtts/u", 0x5be03580, 1, "f,g" }, +{ "cvtts/uc", 0x5be02580, 1, "f,g" }, +{ "cvtts/um", 0x5be02d80, 1, "f,g" }, +{ "cvtts/ud", 0x5be03d80, 1, "f,g" }, +{ "cvtts/su", 0x5be0b580, 1, "f,g" }, +{ "cvtts/suc", 0x5be0a580, 1, "f,g" }, +{ "cvtts/sum", 0x5be0ad80, 1, "f,g" }, +{ "cvtts/sud", 0x5be0bd80, 1, "f,g" }, +{ "cvtts/sui", 0x5be0f580, 1, "f,g" }, +{ "cvtts/suic", 0x5be0e580, 1, "f,g" }, +{ "cvtts/suim", 0x5be0ed80, 1, "f,g" }, +{ "cvtts/suid", 0x5be0fd80, 1, "f,g" }, + +{ "divs", 0x58001060, 1, "e,f,g" }, +{ "divs/c", 0x58000060, 1, "e,f,g" }, +{ "divs/m", 0x58000860, 1, "e,f,g" }, +{ "divs/d", 0x58001860, 1, "e,f,g" }, +{ "divs/u", 0x58003060, 1, "e,f,g" }, +{ "divs/uc", 0x58002060, 1, "e,f,g" }, +{ "divs/um", 0x58002860, 1, "e,f,g" }, +{ "divs/ud", 0x58003860, 1, "e,f,g" }, +{ "divs/su", 0x5800b060, 1, "e,f,g" }, +{ "divs/suc", 0x5800a060, 1, "e,f,g" }, +{ "divs/sum", 0x5800a860, 1, "e,f,g" }, +{ "divs/sud", 0x5800b860, 1, "e,f,g" }, +{ "divs/sui", 0x5800f060, 1, "e,f,g" }, +{ "divs/suic", 0x5800e060, 1, "e,f,g" }, +{ "divs/suim", 0x5800e860, 1, "e,f,g" }, +{ "divs/suid", 0x5800f860, 1, "e,f,g" }, +{ "divt", 0x58001460, 1, "e,f,g" }, +{ "divt/c", 0x58000460, 1, "e,f,g" }, +{ "divt/m", 0x58000c60, 1, "e,f,g" }, +{ "divt/d", 0x58001c60, 1, "e,f,g" }, +{ "divt/u", 0x58003460, 1, "e,f,g" }, +{ "divt/uc", 0x58002460, 1, "e,f,g" }, +{ "divt/um", 0x58002c60, 1, "e,f,g" }, +{ "divt/ud", 0x58003c60, 1, "e,f,g" }, +{ "divt/su", 0x5800b460, 1, "e,f,g" }, +{ "divt/suc", 0x5800a460, 1, "e,f,g" }, +{ "divt/sum", 0x5800ac60, 1, "e,f,g" }, +{ "divt/sud", 0x5800bc60, 1, "e,f,g" }, +{ "divt/sui", 0x5800f460, 1, "e,f,g" }, +{ "divt/suic", 0x5800e460, 1, "e,f,g" }, +{ "divt/suim", 0x5800ec60, 1, "e,f,g" }, +{ "divt/suid", 0x5800fc60, 1, "e,f,g" }, +{ "muls", 0x58001040, 1, "e,f,g" }, +{ "muls/c", 0x58000040, 1, "e,f,g" }, +{ "muls/m", 0x58000840, 1, "e,f,g" }, +{ "muls/d", 0x58001840, 1, "e,f,g" }, +{ "muls/u", 0x58003040, 1, "e,f,g" }, +{ "muls/uc", 0x58002040, 1, "e,f,g" }, +{ "muls/um", 0x58002840, 1, "e,f,g" }, +{ "muls/ud", 0x58003840, 1, "e,f,g" }, +{ "muls/su", 0x5800b040, 1, "e,f,g" }, +{ "muls/suc", 0x5800a040, 1, "e,f,g" }, +{ "muls/sum", 0x5800a840, 1, "e,f,g" }, +{ "muls/sud", 0x5800b840, 1, "e,f,g" }, +{ "muls/sui", 0x5800f040, 1, "e,f,g" }, +{ "muls/suic", 0x5800e040, 1, "e,f,g" }, +{ "muls/suim", 0x5800e840, 1, "e,f,g" }, +{ "muls/suid", 0x5800f840, 1, "e,f,g" }, +{ "mult", 0x58001440, 1, "e,f,g" }, +{ "mult/c", 0x58000440, 1, "e,f,g" }, +{ "mult/m", 0x58000c40, 1, "e,f,g" }, +{ "mult/d", 0x58001c40, 1, "e,f,g" }, +{ "mult/u", 0x58003440, 1, "e,f,g" }, +{ "mult/uc", 0x58002440, 1, "e,f,g" }, +{ "mult/um", 0x58002c40, 1, "e,f,g" }, +{ "mult/ud", 0x58003c40, 1, "e,f,g" }, +{ "mult/su", 0x5800b440, 1, "e,f,g" }, +{ "mult/suc", 0x5800a440, 1, "e,f,g" }, +{ "mult/sum", 0x5800ac40, 1, "e,f,g" }, +{ "mult/sud", 0x5800bc40, 1, "e,f,g" }, +{ "mult/sui", 0x5800f440, 1, "e,f,g" }, +{ "mult/suic", 0x5800e440, 1, "e,f,g" }, +{ "mult/suim", 0x5800ec40, 1, "e,f,g" }, +{ "mult/suid", 0x5800fc40, 1, "e,f,g" }, + +/* + * Miscellaneous + */ +{ "pal", 0x00000000, 0, "I" }, /* 6o+26f */ +{ "call_pal", 0x00000000, 0, "I" }, /* alias */ +{ "bpt", 0x00000080, 0, "" }, +{ "chmk", 0x00000083, 0, "" }, +{ "imb", 0x00000086, 0, "" }, + +{ "draint", 0x60000000, 0, "" }, /* 6o+5a+5b+16d */ +{ "trapb", 0x60000000, 0, "" }, /* 6o+5a+5b+16d */ +{ "fetch", 0x60008000, 0, "0(2)" }, +{ "fetch_m", 0x6000a000, 0, "0(2)" }, +{ "mb", 0x60004000, 0, "" }, +{ "rpcc", 0x6000c000, 0, "1" }, +{ "rc", 0x6000e000, 0, "1" }, +{ "rs", 0x6000f000, 0, "1" }, + +/* + * PAL instructions + */ +{ "hw_ld", 0x6c000000, 0, "1,t(2)" }, +{ "hw_ld/p", 0x6c008000, 0, "1,t(2)" }, +{ "hw_ld/a", 0x6c004000, 0, "1,t(2)" }, +{ "hw_ld/r", 0x6c002000, 0, "1,t(2)" }, +{ "hw_ld/q", 0x6c001000, 0, "1,t(2)" }, +{ "hw_ld/pa", 0x6c00C000, 0, "1,t(2)" }, +{ "hw_ld/pr", 0x6c00A000, 0, "1,t(2)" }, +{ "hw_ld/pq", 0x6c009000, 0, "1,t(2)" }, +{ "hw_ld/ar", 0x6c006000, 0, "1,t(2)" }, +{ "hw_ld/aq", 0x6c005000, 0, "1,t(2)" }, +{ "hw_ld/rq", 0x6c003000, 0, "1,t(2)" }, +{ "hw_ld/par", 0x6c00e000, 0, "1,t(2)" }, +{ "hw_ld/paq", 0x6c00d000, 0, "1,t(2)" }, +{ "hw_ld/prq", 0x6c00b000, 0, "1,t(2)" }, +{ "hw_ld/arq", 0x6c007000, 0, "1,t(2)" }, +{ "hw_ld/parq", 0x6c00f000, 0, "1,t(2)" }, + +{ "hw_ldq", 0x6c001000, 0, "1,t(2)" }, /* ldq/ldl variants for Eric */ +{ "hw_ldq/p", 0x6c009000, 0, "1,t(2)" }, +{ "hw_ldq/a", 0x6c005000, 0, "1,t(2)" }, +{ "hw_ldq/r", 0x6c003000, 0, "1,t(2)" }, +{ "hw_ldq/pa", 0x6c00d000, 0, "1,t(2)" }, +{ "hw_ldq/pr", 0x6c00b000, 0, "1,t(2)" }, +{ "hw_ldq/ar", 0x6c007000, 0, "1,t(2)" }, +{ "hw_ldq/par", 0x6c00f000, 0, "1,t(2)" }, +{ "hw_ldl", 0x6c000000, 0, "1,t(2)" }, +{ "hw_ldl/p", 0x6c008000, 0, "1,t(2)" }, +{ "hw_ldl/a", 0x6c004000, 0, "1,t(2)" }, +{ "hw_ldl/r", 0x6c002000, 0, "1,t(2)" }, +{ "hw_ldl/pa", 0x6c00C000, 0, "1,t(2)" }, +{ "hw_ldl/pr", 0x6c00A000, 0, "1,t(2)" }, +{ "hw_ldl/ar", 0x6c006000, 0, "1,t(2)" }, +{ "hw_ldl/par", 0x6c00e000, 0, "1,t(2)" }, + +{ "hw_st/paq", 0x7c00c000, 0, "1,t(2)" }, +{ "hw_st/pa", 0x7c00b000, 0, "1,t(2)" }, +{ "hw_st/pq", 0x7c009000, 0, "1,t(2)" }, +{ "hw_st/aq", 0x7c005000, 0, "1,t(2)" }, +{ "hw_st/p", 0x7c008000, 0, "1,t(2)" }, +{ "hw_st/a", 0x7c004000, 0, "1,t(2)" }, +{ "hw_st/q", 0x7c001000, 0, "1,t(2)" }, +{ "hw_st", 0x7c000000, 0, "1,t(2)" }, + +{ "hw_stq/pa", 0x7c00c000, 0, "1,t(2)" }, /* stq/stl variants for Eric */ +{ "hw_stq/p", 0x7c009000, 0, "1,t(2)" }, +{ "hw_stq", 0x7c001000, 0, "1,t(2)" }, +{ "hw_stq/a", 0x7c005000, 0, "1,t(2)" }, +{ "hw_stl/pa", 0x7c00b000, 0, "1,t(2)" }, +{ "hw_stl/p", 0x7c008000, 0, "1,t(2)" }, +{ "hw_stl/a", 0x7c004000, 0, "1,t(2)" }, +{ "hw_stl", 0x7c000000, 0, "1,t(2)" }, + +{ "hw_mfpr/p", 0x64000080, 0, "R,3" }, +{ "hw_mfpr/a", 0x64000040, 0, "R,3" }, +{ "hw_mfpr/i", 0x64000020, 0, "R,3" }, +{ "hw_mfpr/pa", 0x640000c0, 0, "R,3" }, +{ "hw_mfpr/pi", 0x640000a0, 0, "R,3" }, +{ "hw_mfpr/ai", 0x64000060, 0, "R,3" }, +{ "hw_mfpr/pai",0x640000e0, 0, "R,3" }, +{ "hw_mfpr", 0x64000000, 0, "R,8" }, + +{ "hw_mtpr/p", 0x74000080, 0, "R,3" }, +{ "hw_mtpr/a", 0x74000040, 0, "R,3" }, +{ "hw_mtpr/i", 0x74000020, 0, "R,3" }, +{ "hw_mtpr/pa", 0x740000c0, 0, "R,3" }, +{ "hw_mtpr/pi", 0x740000a0, 0, "R,3" }, +{ "hw_mtpr/ai", 0x74000060, 0, "R,3" }, +{ "hw_mtpr/pai",0x740000e0, 0, "R,3" }, +{ "hw_mtpr", 0x74000000, 0, "R,8" }, + +{ "hw_rei", 0x7bff8000, 0, "" }, +/* + * More macros + */ +{ "nop", 0x47ff041f, 0, "" }, /* or zero,zero,zero */ +{ "mov", 0x47e00400, 0, "2,3" }, /* or zero,r2,r3 */ +}; + +#define NUMOPCODES ((sizeof alpha_opcodes)/(sizeof alpha_opcodes[0])) + diff --git a/util/alpha-common/include/aout.h b/util/alpha-common/include/aout.h new file mode 100644 index 0000000000..9a73402c9b --- /dev/null +++ b/util/alpha-common/include/aout.h @@ -0,0 +1,221 @@ +/* + * HISTORY + * $Log$ + * Revision 1.1 2001/03/22 21:26:32 rminnich + * testing I HATE CVS + * + * Revision 1.1 2000/03/21 03:56:31 stepan + * Check in current version which is a nearly a 2.2-16 + * + * Revision 1.1 1994/01/31 11:27:45 rusling + * Initial revision + * + * Revision 4.0 1993/10/18 15:37:42 rusling + * Include file. + * + */ +#ifndef _A_OUT_H_ +#define _A_OUT_H_ 1 +/* This file describes the a.out file format + Copyright (C) 1987 Free Software Foundation, Inc. + +This file is part of GAS, the GNU Assembler. + +GAS is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GAS is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + + /* Alpha's a.out. . . */ + +#ifdef CROSS_COMPILE_32_TO_64_BITS +#include "c_32_64.h" +typedef int32 boolean_t; +#else +#include +#endif + +#if __osf__ +typedef long integer_t; +#endif + + +struct exec { + integer_t a_magic; /* Use macros N_MAGIC, etc for access */ + vm_size_t a_text; /* bytes of text in file */ + vm_size_t a_data; /* bytes of data in file */ + vm_size_t a_bss; /* bytes of auto-zeroed data */ + vm_size_t a_syms; /* bytes of symbol table data in file */ + vm_offset_t a_entry; /* start PC */ + vm_offset_t a_tstart; /* text start, in memory */ + vm_offset_t a_dstart; /* data start, in memory */ + vm_size_t a_trsize; /* bytes of text-relocation info in file */ + vm_size_t a_drsize; /* bytes of data-relocation info in file */ +}; + +#define __LDPGSZ 8192 + +#ifndef OMAGIC +#define OMAGIC 0407 +#define NMAGIC 0410 +#define ZMAGIC 0413 +#endif + +#ifdef CROSS_COMPILE_32_TO_64_BITS + +#define N_BADMAG(x) \ + (((x).a_magic.low)!=OMAGIC && ((x).a_magic.low)!=NMAGIC && ((x).a_magic.low)!=ZMAGIC) +/* Address of the bottom of the text segment. */ +#define N_TXTADDR(x) \ + ((x).a_tstart.low) + +/* Address of the bottom of the data segment. */ +#define N_DATADDR(x) \ + ((x).a_dstart.low) + +/* Text segment offset. */ +#define N_TXTOFF(ex) \ + ((ex).a_magic.low == ZMAGIC ? 0 : sizeof(struct exec)) + +/* Data segment offset. */ +#define N_DATOFF(ex) \ + ((N_TXTOFF(ex)) + ((ex).a_magic.low != ZMAGIC ? (ex).a_text.low : \ + __LDPGSZ + ((ex).a_text.low - 1 & ~(__LDPGSZ - 1)))) + +/* Symbol table offset. */ +#define N_SYMOFF(x) \ + (N_TXTOFF(x) + (x).a_text.low + (x).a_data.low + (x).a_trsize.low + (x).a_drsize.low) + +#define N_STROFF(x) \ + (N_SYMOFF(x) + (x).a_syms.low) + +/* text relocation offset */ +#define N_TRELOFF(x) \ + (N_TXTOFF(x) + (x).a_text.low + (x).a_data.low) + +/* data relocation offset */ +#define N_DRELOFF(x) \ + (N_TXTOFF(x) + (x).a_text.low + (x).a_data.low + (x).a_trsize.low) + +#else + +#define N_BADMAG(x) \ + (((x).a_magic)!=OMAGIC && ((x).a_magic)!=NMAGIC && ((x).a_magic)!=ZMAGIC) + +/* Address of the bottom of the text segment. */ +#define N_TXTADDR(x) \ + ((x).a_tstart) + +/* Address of the bottom of the data segment. */ +#define N_DATADDR(x) \ + ((x).a_dstart) + +/* Text segment offset. */ +#define N_TXTOFF(ex) \ + ((ex).a_magic == ZMAGIC ? 0 : sizeof(struct exec)) + +/* Data segment offset. */ +#define N_DATOFF(ex) \ + ((N_TXTOFF(ex)) + ((ex).a_magic != ZMAGIC ? (ex).a_text : \ + __LDPGSZ + ((ex).a_text - 1 & ~(__LDPGSZ - 1)))) + +/* Symbol table offset. */ +#define N_SYMOFF(x) \ + (N_TXTOFF(x) + (x).a_text + (x).a_data + (x).a_trsize + (x).a_drsize) + +#define N_STROFF(x) \ + (N_SYMOFF(x) + (x).a_syms) + +/* text relocation offset */ +#define N_TRELOFF(x) \ + (N_TXTOFF(x) + (x).a_text + (x).a_data) + +/* data relocation offset */ +#define N_DRELOFF(x) \ + (N_TXTOFF(x) + (x).a_text + (x).a_data + (x).a_trsize) + +#endif + +struct nlist { + union { + char *n_name; + struct nlist *n_next; + long n_strx; + vm_offset_t n_pad_cross_compile; + } n_un; + char n_type; + char n_other; + short n_desc; + int n_pad; + vm_offset_t n_value; +}; + +#define N_UNDF 0x0 +#define N_ABS 0x2 +#define N_TEXT 0x4 +#define N_DATA 0x6 +#define N_BSS 0x8 +#define N_COMM 0x12 +#define N_FN 0x1f +#define N_EXT 0x1 +#define N_TYPE 0x1e +#define N_STAB 0xe0 + +#define N_FORMAT "%016lx" + +enum reloc_type +{ + RELOC_0_7, RELOC_0_15, RELOC_0_31, RELOC_0_63, + RELOC_0_25, RELOC_16_31, RELOC_WDISP21, RELOC_BASE21, + RELOC_WDISP14, RELOC_BASE14, RELOC_32_47, RELOC_48_63, + RELOC_U_16_31, RELOC_U_32_47, RELOC_U_48_63, RELOC_0_12, + RELOC_0_8, + + NO_RELOC, + + BRELOC_0_15, BRELOC_0_31, BRELOC_16_31, + BRSET_0_15, BRSET_16_31 +}; + +struct relocation_info { + vm_offset_t r_address; + unsigned int r_index; + unsigned char r_extern; + enum reloc_type r_type : 8; +#ifdef VMS_HOST + short pad; +#endif + integer_t r_addend; +}; + +/* The following constants are used for actually emitting relocation + * information on Alpha. The relocation_info structure can't be used + * directly because the NT compiler alligns structure members in strange + * ways (it appears to allign all members, including fields, on 4 byte + * boundries.). + */ + +#define R_ADDRESS_OFFSET 0 +#define R_ADDRESS_SIZE 8 +#define R_INDEX_OFFSET 8 +#define R_INDEX_SIZE 4 +#define R_EXTERN_OFFSET 12 +#define R_EXTERN_SIZE 1 +#define R_TYPE_OFFSET 13 +#define R_TYPE_SIZE 1 +#define R_ADDEND_OFFSET 16 +#define R_ADDEND_SIZE 8 +#define RELOCATION_INFO_SIZE 24 + +#endif /* _A_OUT_H_ */ + diff --git a/util/alpha-common/include/c_32_64.h b/util/alpha-common/include/c_32_64.h new file mode 100644 index 0000000000..4966d1bb38 --- /dev/null +++ b/util/alpha-common/include/c_32_64.h @@ -0,0 +1,56 @@ +#ifndef _CROSS_H_ +#define _CROSS_H_ 1 + +#ifdef CROSS_COMPILE_32_TO_64_BITS + +#define int16 short int +#define int32 int +typedef struct { + int32 low; + int32 high; +} int64; +#define low32(x) (x).low +#define high32(x) (x).high + +#define _MACHINE_VM_TYPES_H_ 1 +typedef int64 vm_offset_t; +typedef int64 vm_size_t; +typedef int64 integer_t; + +extern int64 zero; +#define neq64(a,b) (((a).low != (b).low) || ((a).high != (b).high)) +#define eq64(a,b) (((a).low == (b).low) && ((a).high == (b).high)) +#define lt64(a,b) (((a).low < (b).low) && ((a).high < (b).high)) +#define assign64(a,b) { (a).low = (b).low; (a).high = (b).high; } +#define assign64h(a,b) (a).high = b +#define assign64l(a,b) (a).low = b +extern int64 plus( int64, int64); +extern int64 minus( int64, int64); +extern int64 plus_a_32( int64, int32); + +#else /* CROSS_COMPILE_32_TO_64_BITS */ + +#ifdef __osf__ +# include +#endif + +#define int16 unsigned short int +#define int32 unsigned int +#define int64 unsigned long int + +#define low32(x) x +#define high32(x) ((x >> 32) & 0xFFFFFFFF) +#define zero 0 +#define neq64(a,b) ((a) != (b)) +#define eq64(a,b) ((a) == (b)) +#define lt64(a,b) ((a) < (b)) +#define assign64(a,b) (a) = (b) +#define assign64h(a,b) a = (a&0xffffffffL) | ((b)<<32) +#define assign64l(a,b) a = (a&0xffffffff00000000L) | (b) +#define plus(a,b) (a) + (b) +#define minus(a,b) (a) - (b) +#define plus_a_32(a,b) (a) + (b) + +#endif /* CROSS_COMPILE_32_TO_64_BITS */ + +#endif /* _CROSS_H_ */ diff --git a/util/alpha-common/include/coff.h b/util/alpha-common/include/coff.h new file mode 100644 index 0000000000..7913ed8d8f --- /dev/null +++ b/util/alpha-common/include/coff.h @@ -0,0 +1,116 @@ +/* + * Mach Operating System + * Copyright (c) 1991,1990,1989 Carnegie Mellon University + * All Rights Reserved. + * + * Permission to use, copy, modify and distribute this software and its + * documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR + * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie Mellon + * the rights to redistribute these changes. + */ +/* + * HISTORY + * 31-May-92 Alessandro Forin (af) at Carnegie-Mellon University + * Adapted for Alpha. + * + * $Log$ + * Revision 1.1 2001/03/22 21:26:32 rminnich + * testing I HATE CVS + * + * Revision 1.1 2000/03/21 03:56:31 stepan + * Check in current version which is a nearly a 2.2-16 + * + * Revision 4.0 1993/10/18 15:37:42 rusling + * Include file. + * + * + */ +/* + * File: coff.h + * Author: Alessandro Forin, Carnegie Mellon University + * Date: 10/89 + * + * Structure definitions for COFF headers + */ + +struct filehdr { + unsigned short f_magic; /* magic number */ + unsigned short f_nscns; /* number of sections */ + int f_timdat; /* time & date stamp */ + unsigned long f_symptr; /* file pointer to symtab */ + int f_nsyms; /* number of symtab entries */ + unsigned short f_opthdr; /* sizeof(optional hdr) */ + unsigned short f_flags; /* flags */ +}; + +#define F_EXEC 0000002 + +#define ALPHAMAGIC 0603 + +struct scnhdr { + char s_name[8]; /* section name */ + unsigned long s_paddr; /* physical address */ + unsigned long s_vaddr; /* virtual address */ + unsigned long s_size; /* section size */ + unsigned long s_scnptr; /* file ptr to raw data for section */ + unsigned long s_relptr; /* file ptr to relocation */ + unsigned long s_lnnoptr; /* file ptr to line numbers */ + unsigned short s_nreloc; /* number of relocation entries */ + unsigned short s_nlnno; /* number of line number entries */ + int s_flags; /* flags */ +}; + + + +struct aouthdr { + short magic; /* see magic.h */ + short vstamp; /* version stamp */ + int pad; /* help for cross compilers */ + unsigned long tsize; /* text size in bytes, padded to FW + bdry */ + unsigned long dsize; /* initialized data " " */ + unsigned long bsize; /* uninitialized data " " */ + unsigned long entry; /* entry point, value of "start"*/ + unsigned long text_start; /* base of text used for this file*/ + unsigned long data_start; /* base of data used for this file*/ + unsigned long bss_start; /* base of bss used for this file */ + int gprmask; /* general purpose register mask*/ + int fprmask; /* FPA register mask */ + unsigned long gp_value; /* the gp value used for this object*/ +}; + + +#define OMAGIC 0407 /* old impure format */ +#define NMAGIC 0410 /* read-only text */ +#define ZMAGIC 0413 /* demand load format */ + +#define N_BADMAG(a) \ + ((a).magic != OMAGIC && (a).magic != NMAGIC && (a).magic != ZMAGIC) + +#define SCNROUND ((long)16) + +struct exechdr { + struct filehdr f; + struct aouthdr a; +}; + +#define N_TXTOFF(f, a) \ + (((a).magic == ZMAGIC) ? 0 : \ + ((sizeof(struct filehdr) + sizeof(struct aouthdr) + \ + (f).f_nscns * sizeof(struct scnhdr) + SCNROUND-1) & ~(SCNROUND -1))) + diff --git a/util/alpha-common/include/dc21064.h b/util/alpha-common/include/dc21064.h new file mode 100644 index 0000000000..6f22928dc3 --- /dev/null +++ b/util/alpha-common/include/dc21064.h @@ -0,0 +1,1059 @@ +#ifndef __DC21064_LOADED +#define __DC21064_LOADED 1 +/* +***************************************************************************** +** * +** Copyright © 1993, 1994 * +** by Digital Equipment Corporation, Maynard, Massachusetts. * +** * +** All Rights Reserved * +** * +** Permission is hereby granted to use, copy, modify and distribute * +** this software and its documentation, in both source code and * +** object code form, and without fee, for the purpose of distribution * +** of this software or modifications of this software within products * +** incorporating an integrated circuit implementing Digital's AXP * +** architecture, regardless of the source of such integrated circuit, * +** provided that the above copyright notice and this permission notice * +** appear in all copies, and that the name of Digital Equipment * +** Corporation not be used in advertising or publicity pertaining to * +** distribution of the document or software without specific, written * +** prior permission. * +** * +** Digital Equipment Corporation disclaims all warranties and/or * +** guarantees with regard to this software, including all implied * +** warranties of fitness for a particular purpose and merchantability, * +** and makes no representations regarding the use of, or the results * +** of the use of, the software and documentation in terms of correctness, * +** accuracy, reliability, currentness or otherwise; and you rely on * +** the software, documentation and results solely at your own risk. * +** * +** AXP is a trademark of Digital Equipment Corporation. * +** * +***************************************************************************** +** +** FACILITY: +** +** DECchip 21064/21066 OSF/1 PALcode +** +** MODULE: +** +** dc21064.h +** +** MODULE DESCRIPTION: +** +** DECchip 21064/21066 specific definitions +** +** AUTHOR: ER +** +** CREATION DATE: 29-Oct-1992 +** +** $Id$ +** +** MODIFICATION HISTORY: +** +** $Log$ +** Revision 1.1 2001/03/22 21:26:32 rminnich +** testing I HATE CVS +** +** Revision 1.1 2000/03/21 03:56:31 stepan +** Check in current version which is a nearly a 2.2-16 +** +** Revision 2.2 1994/06/16 14:47:31 samberg +** For ANSI, changed $ to _, except for pvc and reg def +** +** Revision 2.1 1994/04/01 21:55:51 ericr +** 1-APR-1994 V2 OSF/1 PALcode +** +** Revision 1.6 1994/03/29 20:53:23 ericr +** Fixed comments for ESR mask definitions NOT_CEE and ERR_NOT_CEE +** +** Revision 1.5 1994/03/29 19:32:22 ericr +** Fixed IOC_STAT0 bit definition and mask. +** +** Revision 1.4 1994/03/14 20:45:58 ericr +** Added FPR definitions +** +** Revision 1.3 1994/03/14 16:38:44 samberg +** Use LOAD_REGION_BASE macro instead of individual load_x_csr macros +** +** Revision 1.2 1994/03/08 20:27:52 ericr +** Replaced DEBUG_MONITOR conditional with KDEBUG +** +** Revision 1.1 1994/02/28 18:23:46 ericr +** Initial revision +** +** +*/ + +/*======================================================================*/ +/* INTERNAL PROCESSOR REGISTER DEFINITIONS */ +/*======================================================================*/ + +#define IPR_V_PAL 7 +#define IPR_M_PAL (1< 1 PME1 Performance Monitor Enable 1 +** <44> 1 PME0 Performance Monitor Enable 0 +** <42> 1 FPE Floating Point Enable +** <41> 1 MAP I-stream superpage mapping enable +** <40> 1 HWE Allow PALRES to be issued in kernel mode +** <39> 1 DI Dual Issue enable +** <38> 1 BHE Branch History Enable +** <37> 1 JSE JSR Stack Enable +** <36> 1 BPE Branch Prediction Enable +** <35> 1 PIPE Pipeline enable +** <34:32> 3 MUX1 Performance Counter 1 Select +** <11:08> 3 MUX0 Performance Counter 0 Select +** <3> 1 PC0 Performance Counter 0 Interrupt Enable +** <0> 1 PC1 Performance Counter 1 Interrupt Enable +*/ + +#define ICCSR_V_PME1 45 +#define ICCSR_M_PME1 (1<<(ICCSR_V_PME1-32)) +#define ICCSR_V_PME0 44 +#define ICCSR_M_PME0 (1<<(ICCSR_V_PME0-32)) +#define ICCSR_V_FPE 42 +#define ICCSR_M_FPE (1<<(ICCSR_V_FPE-32)) +#define ICCSR_V_MAP 41 +#define ICCSR_M_MAP (1<<(ICCSR_V_MAP-32)) +#define ICCSR_V_HWE 40 +#define ICCSR_M_HWE (1<<(ICCSR_V_HWE-32)) +#define ICCSR_V_DI 39 +#define ICCSR_M_DI (1<<(ICCSR_V_DI-32)) +#define ICCSR_V_BHE 38 +#define ICCSR_M_BHE (1<<(ICCSR_V_BHE-32)) +#define ICCSR_V_JSE 37 +#define ICCSR_M_JSE (1<<(ICCSR_V_JSE-32)) +#define ICCSR_V_BPE 36 +#define ICCSR_M_BPE (1<<(ICCSR_V_BPE-32)) +#define ICCSR_V_PIPE 35 +#define ICCSR_M_PIPE (1<<(ICCSR_V_PIPE-32)) +#define ICCSR_V_MUX1 32 +#define ICCSR_M_MUX1 (7<<(ICCSR_V_MUX1-32)) +#define ICCSR_V_MUX0 8 +#define ICCSR_M_MUX0 (0xF< 1 MSK Exception Register Write Mask window +** <8> 1 IOV Integer overflow +** <7> 1 INE Inexact result +** <6> 1 UNF Underflow +** <5> 1 OVF Overflow +** <4> 1 DZE Division by zero +** <3> 1 INV Invalid operation +** <2> 1 SWC Software completion +*/ + +#define EXC_V_MSK 33 +#define EXC_M_MSK (1<<(EXC_V_MSK-32)) +#define EXC_V_IOV 8 +#define EXC_M_IOV (1< 1 SLR Serial Line interrupt +** <12:10> 3 IRQ Corresponds to pins Irq_h[2:0] +** <9> 1 PC0 Performance Counter 0 interrupt +** <8> 1 PC1 Performance Counter 1 interrupt +** <7> 1 IRQ5 Corresponds to pin Irq_h[5] +** <6> 1 IRQ4 Corresponds to pin Irq_h[4] +** <5> 1 IRQ3 Corresponds to pin Irq_h[3] +** <4> 1 CRR Correctable read data interrupt +** <3> 1 ATR AST interrupt +** <2> 1 SWR Software interrupt +** <1> 1 HWR Hardware interrupt +*/ +#endif /* DC21064 */ + +#ifdef DC21066 +/* +** Hardware Interrupt Request Register (HIRR) Bit Summary +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <13> 1 SLR Serial Line interrupt +** <12:10> 3 IRQ Corresponds to pins Irq_h[2:0] +** <9> 1 PC0 Performance Counter 0 interrupt +** <8> 1 PC1 Performance Counter 1 interrupt +** <6> 1 MERR Memory error interrupt +** <5> 1 IERR IOC error interrupt +** <4> 1 CRR Correctable read data interrupt +** <3> 1 ATR AST interrupt +** <2> 1 SWR Software interrupt +** <1> 1 HWR Hardware interrupt +*/ +#endif /* DC21066 */ + +#define HIRR_V_SLR 13 +#define HIRR_M_SLR (1< 1 SLE Serial Line interrupt enable +** <15> 1 PC1 Performance Counter 1 interrupt enable +** <14:9> 6 HIER Interrupt enables for Irq_h<5:0> +** <8> 1 PC0 Performance Counter 0 interrupt enable +** <2> 1 CRE Correctable read data interrupt enable +*/ + +#define HIERW_V_SLE 32 +#define HIERW_V_PC1 15 +#define HIERW_V_PC0 8 +#define HIERW_V_CRE 2 +#define HIERW_M_CRE (1< 1 SLC W0C -- Clear serial line int request +** <15> 1 PC1 W0C -- Clear PC1 interrupt request +** <8> 1 PC0 W0C -- Clear PC0 interrupt request +** <2> 1 CRD W0C -- Clear CRD interrupt request +*/ + +#define SL_CLR_V_SLC 32 +#define SL_CLR_V_PC1 15 +#define SL_CLR_V_PC0 8 +#define SL_CLR_V_CRD 2 + +/* +** Abox IPR Definitions +*/ + +#define dtbCtl IPR_M_ABX + 0x0 +#define tbCtl IPR_M_ABX + 0x0 +#define dtbPte IPR_M_ABX + 0x2 +#define dtbPteTemp IPR_M_ABX + 0x3 +#define mmcsr IPR_M_ABX + 0x4 +#define va IPR_M_ABX + 0x5 +#define dtbZap IPR_M_ABX + 0x6 +#define dtbAsm IPR_M_ABX + 0x7 +#define dtbIs IPR_M_ABX + 0x8 + +#ifdef DC21064 +#define biuAddr IPR_M_ABX + 0x9 +#define biuStat IPR_M_ABX + 0xA +#endif /* DC21064 */ + +#define dcAddr IPR_M_ABX + 0xB +#define dcStat IPR_M_ABX + 0xC + +#ifdef DC21064 +#define fillAddr IPR_M_ABX + 0xD +#endif /* DC21064 */ + +#define aboxCtl IPR_M_ABX + 0xE +#define altMode IPR_M_ABX + 0xF +#define cc IPR_M_ABX + 0x10 +#define ccCtl IPR_M_ABX + 0x11 + +#ifdef DC21064 +#define biuCtl IPR_M_ABX + 0x12 +#define fillSyndrome IPR_M_ABX + 0x13 +#define bcTag IPR_M_ABX + 0x14 +#endif /* DC21064 */ + +#define flushIc IPR_M_ABX + 0x15 +#define flushIcAsm IPR_M_ABX + 0x17 +#define xtbZap IPR_M_ABX + IPR_M_IBX + 0x6 +#define xtbAsm IPR_M_ABX + IPR_M_IBX + 0x7 + +/* +** Memory Management Control and Status Register (MM_CSR) Bit Summary +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <14:9> 6 OPC Opcode of faulting instruction +** <8:4> 5 RA Ra field of faulting instruction +** <3> 1 FOW Fault on write +** <2> 1 FOR Fault on read +** <1> 1 ACV Access violation +** <0> 1 WR Faulting reference is a write +*/ + +#define MMCSR_V_OPC 9 +#define MMCSR_M_OPC (0x7E< 1 NOCHK_PAR EV45 - Set to disable checking of +** primary cache parity +** <13> 1 F_TAG_ERR EV45 - Set to generate bad primary +** cache tag parity +** <12> 1 DC_16K EV45 - Set to select 16KB cache +** <11> 1 DC_FHIT Dcache Force Hit +** <10> 1 DC_ENA Dcache Enable +** <6> 1 EMD_EN Limited big endian support enable +** <5> 1 SPE_2 D-stream superpage 1 enable +** <4> 1 SPE_1 D-stream superpage 2 enable +** <3> 1 IC_SBUF_EN Icache Stream Buffer Enable +** <2> 1 CRD_EN Corrected Read Data Enable +** <1> 1 MCHK_EN Machine Check Enable +** <0> 1 WB_DIS Write Buffer unload Disable +*/ + +#define ABOX_V_NOCHK_PAR 14 +#define ABOX_M_NOCHK_PAR (1< 1 IMAP_EN Allow dMapWe<1:0> to assert on +** I-stream backup cache reads +** <37> 1 BYTE_PARITY External byte parity (ignore if ECC set) +** <36> 1 BAD_DP Force bad data parity/ECC check bits +** <35:32> 4 BC_PA_DIS Don't cache PA quadrant specified +** <31> 1 BAD_TCP Force bad tag parity +** <30:28> 3 BC_SIZE External cache size +** <27:13> 16 BC_WE_CTL External cache write enable control +** <11:8> 4 BC_WR_SPD External cache write speed +** <7:4> 4 BC_RD_SPD External cache read speed +** <3> 1 BC_FHIT External cache force hit +** <2> 1 OE Output enable +** <1> 1 ECC Enable ECC +** <0> 1 BC_ENA External cache enable +*/ + +#define BIU_V_IMAP_EN 39 +#define BIU_M_IMAP_EN (1<<(BIU_V_IMAP_EN-32)) +#define BIU_V_BYTE_PARITY 37 +#define BIU_M_BYTE_PARITY (1<<(BIU_V_BYTE_PARITY-32)) +#define BIU_V_BAD_DP 36 +#define BIU_M_BAD_DP (1<<(BIU_V_BAD_DP-32)) +#define BIU_V_BC_PA_DIS 32 +#define BIU_M_BC_PA_DIS (0xF<<(BIU_V_BC_PA_DIS-32)) +#define BIU_V_BAD_TCP 31 +#define BIU_M_BAD_TCP (1<<(BIU_V_BAD_TCP-16)) +#define BIU_V_BC_SIZE 28 +#define BIU_M_BC_SIZE (7<<(BIU_V_BC_SIZE-16)) +#define BIU_V_BC_WE_CTL 13 +#define BIU_M_BC_WE_CTL (0x7FFF< 1 FILL_SEO Second error while FILL_ECC or FILL_DPERR +** <13:12> 2 FILL_QW Used with FILL_ADDR for physical address +** <11> 1 FILL_IRD Icache fill when FILL_ECC or FILL_DPERR +** <10> 1 FILL_DPERR Fill parity error or double bit ECC +** <9> 1 FILL_CRD Corrected read data +** <8> 1 FILL_ECC ECC error +** <7> 1 BIU_SEO Second error while BIU or BC error +** <6:4> 3 BIU_CMD Cycle type +** <3> 1 BC_TCPERR Tag control parity error on external cache +** <2> 1 BC_TPERR Tag address parity error on external cache +** <1> 1 BIU_SERR cAck_h pins indicate SOFT_ERROR +** <0> 1 BIU_HERR cAck_h pins indicate HARD_ERROR +*/ + +#define BIU_STAT_V_FILL_SEO 14 +#define BIU_STAT_M_FILL_SEO (1< 1 IC_ERR EV45 - ICache parity error +** <4> 1 DC_ERR EV45 - DCache parity error +** <3> 1 DC_HIT Dcache hit +** <2:0> 3 EV4 - 111 binary (pass3, i.e. with ECC) +** EV45 - 101 binary +*/ + +#define C_STAT_V_IC_ERR 5 +#define C_STAT_M_IC_ERR (1< to be shifted left 28 bits into <33:28> +*/ + +#define LOAD_REGION_BASE(reg,base) \ + lda reg, base(r31); \ + sll reg, 28, reg + +/* +** Memory Controller (MEM_CTL) Register Definitions +*/ + +#define MEM_CSR_BASE 0x12 /* Bits <33:28> of physical address base */ + +/* +** Offsets to Memory Controller CSRs +*/ + +#define bcr0 0x0 /* Bank Configuration 0 */ +#define bcr1 0x8 /* Bank Configuration 1 */ +#define bcr2 0x10 /* Bank Configuration 2 */ +#define bcr3 0x18 /* Bank Configuration 3 */ +#define bmr0 0x20 /* Bank Mask 0 */ +#define bmr1 0x28 /* Bank Mask 1 */ +#define bmr2 0x30 /* Bank Mask 2 */ +#define bmr3 0x38 /* Bank Mask 3 */ +#define btr0 0x40 /* Bank Timing 0 */ +#define btr1 0x48 /* Bank Timing 1 */ +#define btr2 0x50 /* Bank Timing 2 */ +#define btr3 0x58 /* Bank Timing 3 */ +#define gtr 0x60 /* Global Timing */ +#define esr 0x68 /* Error Status */ +#define ear 0x70 /* Error Address */ +#define car 0x78 /* Backup Cache Control */ +#define vgr 0x80 /* Video and Graphics Control */ +#define plm 0x88 /* Plane Mask */ +#define for 0x90 /* Foreground */ + +/* +** Bank Configuration Register (BCR) Bit Summary +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <28:20> 9 BASE Bank Base Address +** <14> 1 BAV Base Address Valid +** <13> 1 SBE Split (dual) Bank Enable +** <12> 1 BWE Byte Write Enable +** <11> 1 WRM Write Mode +** <10> 1 ERM Error Mode +** <9:6> 4 RAS Row Address Select +*/ + +#define bcr_v_ras 6 +#define bcr_m_ras (0xF< 9 MASK Bank Address Mask +*/ + +#define bmr_v_mask 20 + +/* +** Cache Register (CAR) Bit Summary +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <31> 1 HIT Backup Cache Hit +** <15> 1 PWR Power Saving +** <14> 1 WHD Write Hold Time +** <13:11> 3 WRS Backup Cache Write Speed +** <10:08> 3 RDS Backup Cache Read Speed +** <07:05> 3 SIZE Backup Cache Size +** <4> 1 ECE Backup Cache ECC +** <3> 1 WWP Write Wrong Tag Parity +** <2> 1 ETP Enable Tag Parity +** <0> 1 BCE Backup Cache Enable +*/ + +#define CAR_V_BCE 0 +#define CAR_M_BCE (1< 1 NXM Non-existant memory address +** <11> 1 ICE Ignore corrected errors +** <10> 1 MHE Multiple hard errors +** <9> 1 MSE Multiple soft errors +** <7> 1 CTE Cache tag parity error +** <4> 1 SOR Error source (0=cache, 1=DRAM) +** <3> 1 WRE Error access type (0=read, 1=write) +** <2> 1 UEE Uncorrectable ECC error +** <1> 1 CEE Correctable ECC error +** <0> 1 EAV Error address valid +*/ + +#define ESR_V_NXM 12 +#define ESR_M_NXM (1< of physical address base */ + +/* +** Offsets to I/O controller CSRs +*/ + +#define ioc_hae 0x0 /* Host address extension */ +#define ioc_conf 0x20 /* Configuration cycle type */ +#define ioc_stat0 0x40 /* Error status */ +#define ioc_stat1 0x60 /* Error address */ +#define ioc_tbia 0x80 /* Scatter gather TB invalidate */ +#define ioc_tben 0xa0 /* Scatter gather TB enable */ +#define ioc_pci_rst 0xc0 /* PCI reset */ +#define ioc_w_base0 0x100 /* Window Base 0*/ +#define ioc_w_base1 0x120 /* Window Base 1*/ +#define ioc_w_mask0 0x140 /* Window Mask 0*/ +#define ioc_w_mask1 0x160 /* Window Mask 1*/ +#define ioc_t_base0 0x180 /* Translated Base 0*/ +#define ioc_t_base1 0x1a0 /* Translated Base 1*/ + +/* +** Error Status Register (ESR) Bit Summary +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <31:13> 19 NBR Error address +** <10:8> 3 CODE Error type +** <7> 1 TREF Target window reference indicator +** <6> 1 THIT TB hit indicator +** <5> 1 LOST Lost error +** <4> 1 ERR Error status valid +** <3:0> 4 CMD PCI command field of error cycle +*/ + +#define IOC_V_NBR 13 +#define IOC_V_CODE 8 +#define IOC_M_CODE (7< 1 WEN Window Enable +** <32> 1 SG Scatter Gather Enable +** <31:20> 19 WBASE Window Base +*/ + +#define IOC_V_WEN 33 + +/* +** PCI Reset Bit Summary +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <6> 1 PCI_RST PCI Reset Bit +*/ + +#define IOC_V_PCI_RST 6 +#define IOC_M_PCI_RST 0x4 + +#endif /* DC21066 */ + +/*======================================================================*/ +/* GENERAL PURPOSE REGISTER DEFINITIONS */ +/*======================================================================*/ + +#define r0 $0 +#define r1 $1 +#define r2 $2 +#define r3 $3 +#define r4 $4 +#define r5 $5 +#define r6 $6 +#define r7 $7 +#define r8 $8 +#define r9 $9 +#define r10 $10 +#define r11 $11 +#define r12 $12 +#define r13 $13 +#define r14 $14 +#define r15 $15 +#define r16 $16 +#define r17 $17 +#define r18 $18 +#define r19 $19 +#define r20 $20 +#define r21 $21 +#define r22 $22 +#define r23 $23 +#define r24 $24 +#define r25 $25 +#define r26 $26 +#define r27 $27 +#define r28 $28 +#define r29 $29 +#define r30 $30 +#define r31 $31 + +/*======================================================================*/ +/* FLOATING POINT REGISTER DEFINITIONS */ +/*======================================================================*/ + +#define f0 $f0 +#define f1 $f1 +#define f2 $f2 +#define f3 $f3 +#define f4 $f4 +#define f5 $f5 +#define f6 $f6 +#define f7 $f7 +#define f8 $f8 +#define f9 $f9 +#define f10 $f10 +#define f11 $f11 +#define f12 $f12 +#define f13 $f13 +#define f14 $f14 +#define f15 $f15 +#define f16 $f16 +#define f17 $f17 +#define f18 $f18 +#define f19 $f19 +#define f20 $f20 +#define f21 $f21 +#define f22 $f22 +#define f23 $f23 +#define f24 $f24 +#define f25 $f25 +#define f26 $f26 +#define f27 $f27 +#define f28 $f28 +#define f29 $f29 +#define f30 $f30 +#define f31 $f31 + +/*======================================================================*/ +/* PAL TEMPORARY REGISTER DEFINITIONS */ +/*======================================================================*/ + +#define pt0 IPR_M_PAL + 0x0 +#define pt1 IPR_M_PAL + 0x1 +#define pt2 IPR_M_PAL + 0x2 +#define pt3 IPR_M_PAL + 0x3 +#define pt4 IPR_M_PAL + 0x4 +#define pt5 IPR_M_PAL + 0x5 +#define pt6 IPR_M_PAL + 0x6 +#define pt7 IPR_M_PAL + 0x7 +#define pt8 IPR_M_PAL + 0x8 +#define pt9 IPR_M_PAL + 0x9 +#define pt10 IPR_M_PAL + 0xA +#define pt11 IPR_M_PAL + 0xB +#define pt12 IPR_M_PAL + 0xC +#define pt13 IPR_M_PAL + 0xD +#define pt14 IPR_M_PAL + 0XE +#define pt15 IPR_M_PAL + 0xF +#define pt16 IPR_M_PAL + 0x10 +#define pt17 IPR_M_PAL + 0x11 +#define pt18 IPR_M_PAL + 0x12 +#define pt19 IPR_M_PAL + 0x13 +#define pt20 IPR_M_PAL + 0x14 +#define pt21 IPR_M_PAL + 0x15 +#define pt22 IPR_M_PAL + 0x16 +#define pt23 IPR_M_PAL + 0x17 +#define pt24 IPR_M_PAL + 0x18 +#define pt25 IPR_M_PAL + 0x19 +#define pt26 IPR_M_PAL + 0x1A +#define pt27 IPR_M_PAL + 0x1B +#define pt28 IPR_M_PAL + 0x1C +#define pt29 IPR_M_PAL + 0x1D +#define pt30 IPR_M_PAL + 0x1E +#define pt31 IPR_M_PAL + 0x1F + +/*======================================================================*/ +/* DECchip 21064/21066 Privileged Architecture Library Entry Points */ +/*======================================================================*/ + +/* +** Entry Name Offset (Hex) Length (Instructions) +** +** RESET 0000 8 +** MCHK 0020 16 +** ARITH 0060 32 +** INTERRUPT 00E0 64 +** D_FAULT 01E0 128 +** ITB_MISS 03E0 256 +** ITB_ACV 07E0 64 +** DTB_MISS (Native) 08E0 64 +** DTB_MISS (PAL) 09E0 512 +** UNALIGN 11E0 128 +** OPCDEC 13E0 256 +** FEN 17E0 520 +** CALL_PAL (Privileged) 2000 +** CALL_PAL (Unprivileged) 3000 +*/ + +#define PAL_RESET_ENTRY 0x0000 +#define PAL_MCHK_ENTRY 0x0020 +#define PAL_ARITH_ENTRY 0x0060 +#define PAL_INTERRUPT_ENTRY 0x00E0 +#define PAL_D_FAULT_ENTRY 0x01E0 +#define PAL_ITB_MISS_ENTRY 0x03E0 +#define PAL_ITB_ACV_ENTRY 0x07E0 +#define PAL_NDTB_MISS_ENTRY 0x08E0 +#define PAL_PDTB_MISS_ENTRY 0x09E0 +#define PAL_UNALIGN_ENTRY 0x11E0 +#define PAL_OPCDEC_ENTRY 0x13E0 +#define PAL_FEN_ENTRY 0x17E0 +#define PAL_CALL_PAL_PRIV_ENTRY 0x2000 +#define PAL_CALL_PAL_UNPRIV_ENTRY 0x3000 + +/* +** Architecturally Reserved Opcode Definitions +*/ + +#define mtpr hw_mtpr +#define mfpr hw_mfpr + +#define ldl_a hw_ldl/a +#define ldq_a hw_ldq/a +#define stq_a hw_stq/a +#define stl_a hw_stl/a + +#define ldl_p hw_ldl/p +#define ldq_p hw_ldq/p +#define stl_p hw_stl/p +#define stq_p hw_stq/p + +/* +** Physical mode load-lock and store-conditional variants of +** HW_LD and HW_ST. +*/ + +#define ldl_pa hw_ldl/pa +#define ldq_pa hw_ldq/pa +#define stl_pa hw_stl/pa +#define stq_pa hw_stq/pa + +/* +** This table is an accounting of the DECchip 21064/21066 storage +** used to implement the SRM defined state for OSF/1. +*/ + +#define pt2_iccsr IPR_M_PAL + IPR_M_IBX + 0x2 /* ICCSR shadow register*/ + +#define pt9_ps IPR_M_PAL + IPR_M_IBX + 0x9 /* PS shadow register */ + +#define ptEntInt pt10 /* Entry point to HW interrupt dispatch */ + +#if defined(KDEBUG) + +#define ptEntDbg pt11 /* Entry point to kernel debugger */ + +#endif /* KDEBUG */ + +#define ptEntArith pt12 /* Entry point to arithmetic trap dispatch */ +#define ptEntMM pt13 /* Entry point to MM fault dispatch */ +#define ptEntUna pt14 /* Entry point to unaligned access dispatch */ +#define ptEntSys pt15 /* Entry point to syscall dispatch */ +#define ptEntIF pt16 /* Entry point to instruction fault dispatch*/ +#define ptImpure pt17 /* Pointer to common impure area */ +#define ptUsp pt18 /* User stack pointer */ +#define ptKsp pt19 /* Kernel stack pointer */ +#define ptKgp pt20 /* Kernel global pointer */ + +#define ptIntMask pt22 /* Interrupt enable masks for IRQ_L<7:0> */ + +#define ptSysVal pt24 /* Per-processor system value */ +#define ptMces pt25 /* Machine check error status */ +#define ptWhami pt27 /* Who-Am-I ... and why am I here! ;^) */ +#define ptPtbr pt28 /* Page table base register */ +#define ptVptPtr pt29 /* Virtual page table pointer */ + +#define ptPrevPal pt30 /* Previous PAL base */ +#define ptPrcb pt31 /* Pointer to process control block */ + +#endif /* __DC21064_LOADED */ diff --git a/util/alpha-common/include/dc21164.h b/util/alpha-common/include/dc21164.h new file mode 100644 index 0000000000..f58ed18bcc --- /dev/null +++ b/util/alpha-common/include/dc21164.h @@ -0,0 +1,967 @@ +#ifndef __DC21164_LOADED +#define __DC21164_LOADED 1 +/* +***************************************************************************** +** * +** Copyright © 1993, 1994 * +** by Digital Equipment Corporation, Maynard, Massachusetts. * +** * +** All Rights Reserved * +** * +** Permission is hereby granted to use, copy, modify and distribute * +** this software and its documentation, in both source code and * +** object code form, and without fee, for the purpose of distribution * +** of this software or modifications of this software within products * +** incorporating an integrated circuit implementing Digital's AXP * +** architecture, regardless of the source of such integrated circuit, * +** provided that the above copyright notice and this permission notice * +** appear in all copies, and that the name of Digital Equipment * +** Corporation not be used in advertising or publicity pertaining to * +** distribution of the document or software without specific, written * +** prior permission. * +** * +** Digital Equipment Corporation disclaims all warranties and/or * +** guarantees with regard to this software, including all implied * +** warranties of fitness for a particular purpose and merchantability, * +** and makes no representations regarding the use of, or the results * +** of the use of, the software and documentation in terms of correctness, * +** accuracy, reliability, currentness or otherwise; and you rely on * +** the software, documentation and results solely at your own risk. * +** * +** AXP is a trademark of Digital Equipment Corporation. * +** * +***************************************************************************** +** +** FACILITY: +** +** DECchip 21164 PALcode +** +** MODULE: +** +** dc21164.h +** +** MODULE DESCRIPTION: +** +** DECchip 21164 specific definitions +** +** AUTHOR: ER +** +** CREATION DATE: 24-Nov-1993 +** +** $Id$ +** +** MODIFICATION HISTORY: +** +** $Log$ +** Revision 1.1 2001/03/22 21:26:32 rminnich +** testing I HATE CVS +** +** Revision 1.1 2000/03/21 03:56:31 stepan +** Check in current version which is a nearly a 2.2-16 +** +** Revision 1.15 1995/04/21 02:06:30 fdh +** Replaced C++ style comments with Standard C style comments. +** +** Revision 1.14 1995/03/20 14:55:23 samberg +** Add flushIc to make Roger Cruz's life easier. +** +** Revision 1.13 1994/12/14 15:52:48 samberg +** Add slXmit and slRcv bit definitions +** +** Revision 1.12 1994/09/07 15:43:49 samberg +** Changes for Makefile.vpp, take out OSF definition +** +** Revision 1.11 1994/07/26 17:38:35 samberg +** Changes for SD164. +** +** Revision 1.10 1994/07/08 17:02:12 samberg +** Changes to support platform specific additions +** +** Revision 1.8 1994/05/31 15:49:21 ericr +** Moved ptKdebug from pt10 to pt13; pt10 is used in MCHK flows +** +** Revision 1.7 1994/05/26 19:29:51 ericr +** Added BC_CONFIG definitions +** +** Revision 1.6 1994/05/25 14:27:25 ericr +** Added physical bit to ldq_lp and stq_cp macros +** +** Revision 1.5 1994/05/20 18:07:50 ericr +** Changed line comments to C++ style comment character +** +** Revision 1.4 1994/01/17 21:46:54 ericr +** Added floating point register definitions +** +** Revision 1.3 1994/01/03 19:31:49 ericr +** Added cache parity error status register definitions +** +** Revision 1.2 1993/12/22 20:42:35 eric +** Added ptTrap, ptMisc and flag definitions +** Added PAL shadow regsiter definitions +** +** Revision 1.1 1993/12/16 21:55:05 eric +** Initial revision +** +** +**-- +*/ + + +/* +** +** INTERNAL PROCESSOR REGISTER DEFINITIONS +** +** The internal processor register definitions below are annotated +** with one of the following symbols: +** +** RW - The register may be read and written +** RO - The register may only be read +** WO - The register may only be written +** +** For RO and WO registers, all bits and fields within the register are +** also read-only or write-only. For RW registers, each bit or field +** within the register is annotated with one of the following: +** +** RW - The bit/field may be read and written +** RO - The bit/field may be read; writes are ignored +** WO - The bit/field may be written; reads return UNPREDICTABLE +** WZ - The bit/field may be written; reads return a zero value +** W0C - The bit/field may be read; write-zero-to-clear +** W1C - The bit/field may be read; write-one-to-clear +** WA - The bit/field may be read; write-anything-to-clear +** RC - The bit/field may be read, causing state to clear; +** writes are ignored +** +*/ + + +/* +** +** Ibox IPR Definitions: +** +*/ + +#define isr 0x100 /* RO - Interrupt Summary */ +#define itbTag 0x101 /* WO - ITB Tag */ +#define itbPte 0x102 /* RW - ITB Page Table Entry */ +#define itbAsn 0x103 /* RW - ITB Address Space Number */ +#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */ +#define itbIa 0x105 /* WO - ITB Invalidate All */ +#define itbIap 0x106 /* WO - ITB Invalidate All Process */ +#define itbIs 0x107 /* WO - ITB Invalidate Single */ +#define sirr 0x108 /* RW - Software Interrupt Request */ +#define astrr 0x109 /* RW - Async. System Trap Request */ +#define aster 0x10A /* RW - Async. System Trap Enable */ +#define excAddr 0x10B /* RW - Exception Address */ +#define excSum 0x10C /* RW - Exception Summary */ +#define excMask 0x10D /* RO - Exception Mask */ +#define palBase 0x10E /* RW - PAL Base */ +#define ips 0x10F /* RW - Processor Status */ +#define ipl 0x110 /* RW - Interrupt Priority Level */ +#define intId 0x111 /* RO - Interrupt ID */ +#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */ +#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */ +#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */ +#define slXmit 0x116 /* WO - Serial Line Transmit */ +#define slRcv 0x117 /* RO - Serial Line Receive */ +#define icsr 0x118 /* RW - Ibox Control/Status */ +#define icFlush 0x119 /* WO - I-Cache Flush Control */ +#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */ +#define icPerr 0x11A /* RW - I-Cache Parity Error Status */ +#define PmCtr 0x11C /* RW - Performance Counter */ + +/* +** +** Ibox Control/Status Register (ICSR) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- ------------------------------------ +** <39> 1 TST RW,0 Assert Test Status +** <38> 1 ISTA RO I-Cache BIST Status +** <37> 1 DBS RW,1 Debug Port Select +** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity +** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity +** <34> 1 FMS RW,0 Force I-Cache Miss +** <33> 1 SLE RW,0 Enable Serial Line Interrupts +** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts +** <30> 1 SDE RW,0 Enable PAL Shadow Registers +** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode +** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode +** <26> 1 FPE RW,0 Enable Floating Point Instructions +** <25> 1 TMD RW,0 Disable Ibox Timeout Counter +** <24> 1 TMM RW,0 Timeout Counter Mode +** +*/ + +#define ICSR_V_TST 39 +#define ICSR_M_TST (1< 1 TMT WO,1 Serial line transmit data +** +*/ + +#define SLXMIT_V_TMT 7 +#define SLXMIT_M_TMT (1< 1 RCV RO Serial line receive data +** +*/ + +#define SLRCV_V_RCV 6 +#define SLRCV_M_RCV (1< 1 TMR W1C Timeout reset error +** <12> 1 TPE W1C Tag parity error +** <11> 1 DPE W1C Data parity error +** +*/ + +#define ICPERR_V_TMR 13 +#define ICPERR_M_TMR (1< 1 IOV WA Integer overflow +** <15> 1 INE WA Inexact result +** <14> 1 UNF WA Underflow +** <13> 1 FOV WA Overflow +** <12> 1 DZE WA Division by zero +** <11> 1 INV WA Invalid operation +** <10> 1 SWC WA Software completion +** +*/ + +#define EXC_V_IOV 16 +#define EXC_M_IOV (1< 1 SLC W1C Clear Serial Line interrupt +** <32> 1 CRDC W1C Clear Correctable Read Data interrupt +** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt +** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt +** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt +** +*/ + +#define HWINT_V_SLC 33 +#define HWINT_M_SLC (1< 1 HLT RO External Halt interrupt +** <33> 1 SLI RO Serial Line interrupt +** <32> 1 CRD RO Correctable ECC errors +** <31> 1 MCK RO System Machine Check +** <30> 1 PFL RO Power Fail +** <29> 1 PC2 RO Performance Counter 2 interrupt +** <28> 1 PC1 RO Performance Counter 1 interrupt +** <27> 1 PC0 RO Performance Counter 0 interrupt +** <23> 1 I23 RO External Hardware interrupt +** <22> 1 I22 RO External Hardware interrupt +** <21> 1 I21 RO External Hardware interrupt +** <20> 1 I20 RO External Hardware interrupt +** <19> 1 ATR RO Async. System Trap request +** <18:4> 15 SIRR RO,0 Software Interrupt request +** <3:0> 4 ASTRR RO Async. System Trap request (USEK) +** +**/ + +#define ISR_V_HLT 34 +#define ISR_M_HLT (1< 6 OPCODE RO Opcode of faulting instruction +** <10:06> 5 RA RO Ra field of faulting instruction +** <5> 1 BAD_VA RO Bad virtual address +** <4> 1 DTB_MISS RO Reference resulted in DTB miss +** <3> 1 FOW RO Fault on write +** <2> 1 FOR RO Fault on read +** <1> 1 ACV RO Access violation +** <0> 1 WR RO Reference type +** +*/ + +#define MMSTAT_V_OPC 11 +#define MMSTAT_M_OPC (0x3F< 1 DBG1 RW,0 Mbox Debug Packet Select +** <4> 1 E_BE RW,0 Ebox Big Endian mode enable +** <3> 1 DBG0 RW,0 Debug Test Select +** <2:1> 2 SP RW,0 Superpage mode enable +** <0> 1 M_BE RW,0 Mbox Big Endian mode enable +** +*/ + +#define MCSR_V_DBG1 5 +#define MCSR_M_DBG1 (1< 1 TP1 RO Dcache bank 1 tag parity error +** <4> 1 TP0 RO Dcache bank 0 tag parity error +** <3> 1 DP1 RO Dcache bank 1 data parity error +** <2> 1 DP0 RO Dcache bank 0 data parity error +** <1> 1 LOCK W1C Locks/clears bits <5:2> +** <0> 1 SEO W1C Second Dcache parity error occurred +** +*/ + +#define DCPERR_V_TP1 5 +#define DCPERR_M_TP1 (1< 1 DOA RO Hardware Dcache Disable +** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting +** <2> 1 BAD_DP RW,0 Force Dcache data bad parity +** <1> 1 FHIT RW,0 Force Dcache hit +** <0> 1 ENA RW,0 Software Dcache Enable +** +*/ + +#define DC_V_DOA 4 +#define DC_M_DOA (1< 1 WB RO,0 If set, pending WB request +** <6> 1 DREAD RO,0 If set, pending D-read request +** +*/ + +#define MAF_V_WB_PENDING 7 +#define MAF_M_WB_PENDING (1< 3 SET_EN RW,1 Set enable +** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select +** <11:08> 4 FB_DP RW,0 Force bad data parity +** <07:02> 6 TAG_STAT RW Tag status and parity +** <1> 1 FLUSH RW,0 If set, clear all tag valid bits +** <0> 1 FHIT RW,0 Force hits +** +*/ + +#define SC_V_SET_EN 13 +#define SC_M_SET_EN (7< 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer +** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads +** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select +** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select +** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining +** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins +** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error +** <14:13> 2 BC_BAD_DAT WO,0 Force bad data +** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity +** <7> 1 BC_FHIT WO,0 Bcache force hit +** <6> 1 EI_ECC WO,1 ECC or byte parity mode +** <5> 1 VTM_FIRST WO,1 Drive out victim block address first +** <4> 1 CORR_FILL_DAT WO,1 Correct fill data +** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins +** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins +** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs. +** <0> 1 BC_ENA W0,0 Bcache enable +** +*/ +#define BC_V_DIS_SC_VIC_BUF 27 +#define BC_M_DIS_SC_VIC_BUF (1<>1) +/* +** +** Bcache Configuration Register (BC_CONFIG) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- --------------------------------- +** <35:29> 7 RSVD WO Reserved - Must Be Zero +** <28:20> 9 WE_CTL WO,0 Bcache write enable control +** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero +** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset +** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero +** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing +** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles +** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles +** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero +** <02:00> 3 SIZE WO,1 Bcache size +*/ +#define BC_V_WE_CTL 20 +#define BC_M_WE_CTL (0x1FF< = 1. +*/ + +#define p0 r8 /* ITB/DTB Miss Scratch */ +#define p1 r9 /* ITB/DTB Miss Scratch */ +#define p2 r10 /* ITB/DTB Miss Scratch */ +#define p3 r11 +#define ps r11 /* Processor Status */ +#define p4 r12 /* Local Scratch */ +#define p5 r13 /* Local Scratch */ +#define p6 r14 /* Local Scratch */ +#define p7 r25 /* Local Scratch */ + +/* +** SRM Defined State Definitions: +*/ + +/* +** This table is an accounting of the DECchip 21164 storage used to +** implement the SRM defined state for OSF/1. +** +** IPR Name Internal Storage +** -------- ---------------- +** Processor Status ps, dtbCm, ipl, r11 +** Program Counter Ibox +** Interrupt Entry ptEntInt +** Arith Trap Entry ptEntArith +** MM Fault Entry ptEntMM +** Unaligned Access Entry ptEntUna +** Instruction Fault Entry ptEntIF +** Call System Entry ptEntSys +** User Stack Pointer ptUsp +** Kernel Stack Pointer ptKsp +** Kernel Global Pointer ptKgp +** System Value ptSysVal +** Page Table Base Register ptPtbr +** Virtual Page Table Base iVptBr, mVptBr +** Process Control Block Base ptPcbb +** Address Space Number itbAsn, dtbAsn +** Cycle Counter cc, ccCtl +** Float Point Enable icsr +** Lock Flag Cbox/System +** Unique PCB +** Who-Am-I ptWhami +*/ + +#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */ +#define ptImpure pt3 /* Pointer To PAL Scratch Area */ +#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */ +#define ptIntMask pt8 /* Interrupt Enable Mask */ +#define ptEntSys pt9 /* Call System Dispatch Entry */ +#define ptTrap pt11 +#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */ +#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */ +#if defined(KDEBUG) +#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */ +#endif /* KDEBUG */ +#define ptMisc pt16 /* Miscellaneous Flags */ +#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */ +#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */ +#define ptSysVal pt17 /* Per-Processor System Value */ +#define ptUsp pt18 /* User Stack Pointer */ +#define ptKsp pt19 /* Kernel Stack Pointer */ +#define ptPtbr pt20 /* Page Table Base Register */ +#define ptEntMM pt21 /* MM Fault Dispatch Entry */ +#define ptKgp pt22 /* Kernel Global Pointer */ +#define ptPcbb pt23 /* Process Control Block Base */ + +/* +** +** Miscellaneous PAL State Flags (ptMisc) Bit Summary +** +** Extent Size Name Function +** ------ ---- ---- --------------------------------- +** <55:48> 8 SWAP Swap PALcode flag -- character 'S' +** <47:32> 16 MCHK Machine Check Error code +** <31:16> 16 SCB System Control Block vector +** <15:08> 8 WHAMI Who-Am-I identifier +** <04:00> 5 MCES Machine Check Error Summary bits +** +*/ + +#define PT16_V_MCES 0 +#define PT16_V_WHAMI 8 +#define PT16_V_SCB 16 +#define PT16_V_MCHK 32 +#define PT16_V_SWAP 48 + +#endif /* __DC21164_LOADED */ + + + + + diff --git a/util/alpha-common/include/exec.h b/util/alpha-common/include/exec.h new file mode 100644 index 0000000000..bd1b506661 --- /dev/null +++ b/util/alpha-common/include/exec.h @@ -0,0 +1,74 @@ +/* + * Mach Operating System + * Copyright (c) 1992 Carnegie Mellon University + * All Rights Reserved. + * + * Permission to use, copy, modify and distribute this software and its + * documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR + * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie Mellon + * the rights to redistribute these changes. + */ +/* + * HISTORY + * $Log$ + * Revision 1.1 2001/03/22 21:26:32 rminnich + * testing I HATE CVS + * + * Revision 1.1 2000/03/21 03:56:31 stepan + * Check in current version which is a nearly a 2.2-16 + * + * Revision 4.0 1993/10/18 15:37:42 rusling + * Include file. + * + * Revision 4.0 1993/10/18 14:38:36 rusling + * *** empty log message *** + * + */ +/* + * exec stucture in an a.out file derived from FSF's + * a.out.gnu.h file. + */ + +#ifndef _ALPHA_EXEC_H_ +#define _ALPHA_EXEC_H_ + +/* + * Header prepended to each a.out file. + */ +struct exec +{ + integer_t a_magic; /* Use macros N_MAGIC, etc for access */ + vm_size_t a_text; /* bytes of text in file */ + vm_size_t a_data; /* bytes of data in file */ + vm_size_t a_bss; /* bytes of auto-zeroed data */ + vm_size_t a_syms; /* bytes of symbol table data in file */ + vm_offset_t a_entry; /* start PC */ + vm_offset_t a_tstart; /* text start, in memory */ + vm_offset_t a_dstart; /* data start, in memory */ + vm_size_t a_trsize; /* bytes of text-relocation info in file */ + vm_size_t a_drsize; /* bytes of data-relocation info in file */ +}; + +/* Code indicating object file or impure executable. */ +#define OMAGIC 0407 +/* Code indicating pure executable. */ +#define NMAGIC 0410 +/* Code indicating demand-paged executable. */ +#define ZMAGIC 0413 + +#endif _ALPHA_EXEC_H_ diff --git a/util/alpha-common/include/local.h b/util/alpha-common/include/local.h new file mode 100644 index 0000000000..0968bb55f8 --- /dev/null +++ b/util/alpha-common/include/local.h @@ -0,0 +1,100 @@ +#ifndef __LOCAL_H_LOADED +#define __LOCAL_H_LOADED +/***************************************************************************** + + Copyright © 1993, 1994 Digital Equipment Corporation, + Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, provided +that the copyright notice and this permission notice appear in all copies +of software and supporting documentation, and that the name of Digital not +be used in advertising or publicity pertaining to distribution of the software +without specific, written prior permission. Digital grants this permission +provided that you prominently mark, as not part of the original, any +modifications made to this software or documentation. + +Digital Equipment Corporation disclaims all warranties and/or guarantees +with regard to this software, including all implied warranties of fitness for +a particular purpose and merchantability, and makes no representations +regarding the use of, or the results of the use of, the software and +documentation in terms of correctness, accuracy, reliability, currentness or +otherwise; and you rely on the software, documentation and results solely at +your own risk. + +******************************************************************************/ + +/* + * $Id$; + */ + +/* + * $Log$ + * Revision 1.1 2001/03/22 21:26:32 rminnich + * testing I HATE CVS + * + * Revision 1.1 2000/03/21 03:56:31 stepan + * Check in current version which is a nearly a 2.2-16 + * + * Revision 1.3 1995/02/27 21:27:56 fdh + * Include + * + * Revision 1.2 1995/02/10 02:03:16 fdh + * Added definitions for TRUE and FALSE. + * + * Revision 1.1 1995/02/07 00:44:43 fdh + * Initial revision + * + */ + +/* + * Source files that are common between the ebfw source + * tree and the ebtools source tree could have inherent + * conflicts in their requirements for libraries, definitions, + * etc. The basic difference is that ebtools are built + * to run natively with an operating system where the ebfw + * tree is built to run in a freestanding environment on, + * typically, an evaluation board target. Therefore, this + * file is used to provide the proper environment for building + * those common files in the ebtools source tree. + */ + +#include +#include +#include +#include "c_32_64.h" + +#define ub unsigned char +#define uw unsigned short int + +#ifdef CROSS_COMPILE_32_TO_64_BITS + +#define ui unsigned int +#define sl int64 +#define ul int64 + +#else /* CROSS_COMPILE_32_TO_64_BITS */ + +#ifdef _WIN32 +#define ul unsigned __int64 +#define sl __int64 +#define ui unsigned long +#else +#define ul unsigned long +#define sl long +#define ui unsigned int +#endif + +#endif /* CROSS_COMPILE_32_TO_64_BITS */ + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#endif /* __LOCAL_H_LOADED */ diff --git a/util/alpha-common/include/paldefs.h b/util/alpha-common/include/paldefs.h new file mode 100644 index 0000000000..a40d6252dc --- /dev/null +++ b/util/alpha-common/include/paldefs.h @@ -0,0 +1,79 @@ +#ifndef __PALDEFS_H_LOADED +#define __PALDEFS_H_LOADED +/***************************************************************************** + + Copyright © 1993, 1994 Digital Equipment Corporation, + Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, provided +that the copyright notice and this permission notice appear in all copies +of software and supporting documentation, and that the name of Digital not +be used in advertising or publicity pertaining to distribution of the software +without specific, written prior permission. Digital grants this permission +provided that you prominently mark, as not part of the original, any +modifications made to this software or documentation. + +Digital Equipment Corporation disclaims all warranties and/or guarantees +with regard to this software, including all implied warranties of fitness for +a particular purpose and merchantability, and makes no representations +regarding the use of, or the results of the use of, the software and +documentation in terms of correctness, accuracy, reliability, currentness or +otherwise; and you rely on the software, documentation and results solely at +your own risk. + +******************************************************************************/ + +/* + * $Id$; + */ + +/* + * $Log$ + * Revision 1.1 2001/03/22 21:26:32 rminnich + * testing I HATE CVS + * + * Revision 1.1 2000/03/21 03:56:31 stepan + * Check in current version which is a nearly a 2.2-16 + * + * Revision 1.1 1995/02/24 15:54:10 fdh + * Initial revision + * + */ + +#define PAL_halt 0x0000 +#define PAL_cflush 0x0001 +#define PAL_draina 0x0002 +#define PAL_cobratt 0x0009 +#define PAL_ipir 0x000d +#define PAL_mtpr_mces 0x0011 +#define PAL_wrfen 0x002b +#define PAL_wrvptptr 0x002d +#define PAL_jtopal 0x002e +#define PAL_swpctx 0x0030 +#define PAL_wrval 0x0031 +#define PAL_rdval 0x0032 +#define PAL_tbi 0x0033 +#define PAL_wrent 0x0034 +#define PAL_swpipl 0x0035 +#define PAL_rdps 0x0036 +#define PAL_wrkgp 0x0037 +#define PAL_wrusp 0x0038 +#define PAL_wrperfmon 0x0039 +#define PAL_rdusp 0x003a +#define PAL_whami 0x003c +#define PAL_rtsys 0x003d +#define PAL_rti 0x003f +#define PAL_bpt 0x0080 +#define PAL_bugchk 0x0081 +#define PAL_chmk 0x0083 +#define PAL_callsys 0x0083 +#define PAL_imb 0x0086 +#define PAL_rduniq 0x009e +#define PAL_wruniq 0x009f +#define PAL_gentrap 0x00aa +#define PAL_nphalt 0x00be + +#endif /* __PALDEFS_H_LOADED */ diff --git a/util/alpha-common/include/regdefs.h b/util/alpha-common/include/regdefs.h new file mode 100644 index 0000000000..beddf9a063 --- /dev/null +++ b/util/alpha-common/include/regdefs.h @@ -0,0 +1,86 @@ +#ifndef __REGDEFS_H_LOADED +#define __REGDEFS_H_LOADED +/***************************************************************************** + + Copyright © 1993, 1994 Digital Equipment Corporation, + Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, provided +that the copyright notice and this permission notice appear in all copies +of software and supporting documentation, and that the name of Digital not +be used in advertising or publicity pertaining to distribution of the software +without specific, written prior permission. Digital grants this permission +provided that you prominently mark, as not part of the original, any +modifications made to this software or documentation. + +Digital Equipment Corporation disclaims all warranties and/or guarantees +with regard to this software, including all implied warranties of fitness for +a particular purpose and merchantability, and makes no representations +regarding the use of, or the results of the use of, the software and +documentation in terms of correctness, accuracy, reliability, currentness or +otherwise; and you rely on the software, documentation and results solely at +your own risk. + +******************************************************************************/ + +/* + * $Id$; + */ + +/* + * $Log$ + * Revision 1.1 2001/03/22 21:26:32 rminnich + * testing I HATE CVS + * + * Revision 1.1 2000/03/21 03:56:31 stepan + * Check in current version which is a nearly a 2.2-16 + * + * Revision 1.2 1995/02/24 16:00:18 fdh + * Conditional around #define AT. + * + * Revision 1.1 1995/02/24 15:54:26 fdh + * Initial revision + * + */ + +#define v0 $0 +#define t0 $1 +#define t1 $2 +#define t2 $3 +#define t3 $4 +#define t4 $5 +#define t5 $6 +#define t6 $7 +#define t7 $8 +#define s0 $9 +#define s1 $10 +#define s2 $11 +#define s3 $12 +#define s4 $13 +#define s5 $14 +#define s6 $15 +#define fp $15 /* fp & s6 are the same */ +#define a0 $16 +#define a1 $17 +#define a2 $18 +#define a3 $19 +#define a4 $20 +#define a5 $21 +#define t8 $22 +#define t9 $23 +#define t10 $24 +#define t11 $25 +#define ra $26 +#define pv $27 /* pv and t5 are the same */ +#define t12 $27 +#ifndef AT +#define AT $at +#endif +#define gp $29 +#define sp $30 +#define zero $31 + +#endif /* __REGDEFS_H_LOADED */ diff --git a/util/alpha-common/include/reloc.h b/util/alpha-common/include/reloc.h new file mode 100644 index 0000000000..6c8d3c3c68 --- /dev/null +++ b/util/alpha-common/include/reloc.h @@ -0,0 +1,116 @@ +struct reloc { + long r_vaddr; /* (virtual) address of reference */ + unsigned r_symndx; /* index into symbol table */ + unsigned r_type : 8; /* relocation type */ + unsigned r_extern: 1; /* if 1 symndx is an index into the external + symbol table, else symndx is a section # */ + + unsigned r_offset:6; /* for R_OP_STORE, quad based LE bit offset */ + unsigned r_reserved:11; /* Must be zero */ + unsigned r_size:6; /* R_OP_STORE, bit size */ +}; +#define RELOC struct reloc +#define RELSZ sizeof(RELOC) + + +/* + * ALPHA machines r_type values + * + * reloc. already performed to symbol in the same section + * 32-bit reference + * 64-bit reference + * 32-bit displacement from gp + * reference to global pointer relative literal pool item + * identifies useage of a literal address previously loaded + * lda/ldah instruction pair to initialize gp. + * 21-bit branch reference + * 14-bit jsr hint reference + */ + +#define R_ABS 0 +#define R_REFLONG 1 +#define R_REFQUAD 2 +#define R_GPREL32 3 +#define R_LITERAL 4 +#define R_LITUSE 5 +#define R_GPDISP 6 +#define R_BRADDR 7 +#define R_HINT 8 +/* + * self relative relocations mean that the memory location at + * r_vaddr contains an offset to the destination. If the relocation + * is r_extern==1, then the value at the memory location is ignored + * (maybe we should allow offsets?). If r_extern==0, then the value + * at the memory location is the actual offset. + * + * The linker uses the relocated target and a relocated r_vaddr to + * determine the offset. Offsets are considered signed. + */ +#define R_SREL16 9 /* self relative 16 bit offset */ +#define R_SREL32 10 /* self relative 32 bit offset */ +#define R_SREL64 11 /* self relative 64 bit offset */ +/* + * stack relocations provide a primitive expression evaluator for + * relocatable and constant values at link time. It also provides + * a way to store a value into a bit field (the R_OP_STORE has a + * bit size and offset field (from a quadword aligned qaudword)). + * + * The operations specify what they relocate and what happens to + * the linktime stack. It is an error to cause a stack underflow + * or have values left on the stack when the relocation for a section + * is complete. + * + * terms: + * tos top of stack + * stack qaudword array representing the stack + * vaddr address field in reloc record or + * extern symbol address + * relocate(X) relocate address X + * X(o:s) address X, bitoffset o, bit size s + * r_offset offset field in reloc record + * r_size bitsize field in reloc record + * + * Note: use R_SN_ABS as the section for constants (like in shifts). + * + */ +#define R_OP_PUSH 12 /* stack[++tos] = relocate(vaddr) */ +#define R_OP_STORE 13 /* vaddr(r_offset:r_size) = stack[tos--] */ +#define R_OP_PSUB 14 /* stack[tos] = stack[tos] - relocate(vaddr) */ +#define R_OP_PRSHIFT 15 /* stack[tos] = stack[tos] >> relocate(vaddr) */ + +#define MAX_R_TYPE 16 + +/* + * Section numbers for symndex for local relocation entries (r_extern == 0). + * For these entries the starting address for the section referenced by the + * section number is used in place of an external symbol table entry's value. + */ +#define R_SN_NULL 0 +#define R_SN_TEXT 1 +#define R_SN_RDATA 2 +#define R_SN_DATA 3 +#define R_SN_SDATA 4 +#define R_SN_SBSS 5 +#define R_SN_BSS 6 +#define R_SN_INIT 7 +#define R_SN_LIT8 8 +#define R_SN_LIT4 9 +#define R_SN_XDATA 10 +#define R_SN_PDATA 11 +#define R_SN_FINI 12 +#define R_SN_LITA 13 +#define R_SN_ABS 14 /* constant relocation r_vaddr's */ +#define MAX_R_SN 14 + +/* + * symindex values when type is R_LITUSE + * + * literal address in register of a memory format instruction + * literal address in byte offset register of byte-manipulation instruction + * literal address is in target register of a jsr instruction. + */ + +#define R_LU_BASE 1 +#define R_LU_BYTOFF 2 +#define R_LU_JSR 3 + diff --git a/util/alpha-common/include/romhead.h b/util/alpha-common/include/romhead.h new file mode 100644 index 0000000000..e726ea8801 --- /dev/null +++ b/util/alpha-common/include/romhead.h @@ -0,0 +1,357 @@ +#ifndef __ROMHEAD_H_LOADED +#define __ROMHEAD_H_LOADED +/***************************************************************************** + + Copyright © 1993, 1994 Digital Equipment Corporation, + Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, provided +that the copyright notice and this permission notice appear in all copies +of software and supporting documentation, and that the name of Digital not +be used in advertising or publicity pertaining to distribution of the software +without specific, written prior permission. Digital grants this permission +provided that you prominently mark, as not part of the original, any +modifications made to this software or documentation. + +Digital Equipment Corporation disclaims all warranties and/or guarantees +with regard to this software, including all implied warranties of fitness for +a particular purpose and merchantability, and makes no representations +regarding the use of, or the results of the use of, the software and +documentation in terms of correctness, accuracy, reliability, currentness or +otherwise; and you rely on the software, documentation and results solely at +your own risk. + +******************************************************************************/ + +/* + * $Id$; + */ + +/* + * $Log$ + * Revision 1.1 2001/03/22 21:26:32 rminnich + * testing I HATE CVS + * + * Revision 1.1 2000/03/21 03:56:31 stepan + * Check in current version which is a nearly a 2.2-16 + * + * Revision 1.16 1995/03/05 00:51:01 fdh + * Fixed up a couple of MACROS. + * + * Revision 1.15 1995/03/04 05:55:57 fdh + * Bracket COMPUTE_CHECKSUM Macro. + * + * Revision 1.14 1995/02/27 15:36:21 fdh + * Removed ul definitions. Replaced with structs of ui's. + * + * Revision 1.13 1995/02/16 22:06:06 fdh + * Changed Open VMS to OpenVMS because of some trademark junk. + * + * Revision 1.12 1995/02/14 21:19:33 cruz + * Fixed up header picture to match implementation. + * + * Revision 1.11 1995/02/10 02:19:03 fdh + * Created COMPUTE_CHECKSUM Macro. + * Corrected prototypes. + * + * Revision 1.10 1995/02/08 00:34:44 fdh + * Added ROMH_VERSION and ROTATE_RIGHT macros. + * + * Revision 1.9 1995/02/07 22:28:09 fdh + * Changed Windows NT alias from "WNT" to "NT". + * + * Revision 1.8 1995/02/07 04:54:33 fdh + * Added ostype definitions. + * Modified ROM_HEADER_CHECKSUM Macro. + * + * Revision 1.7 1995/02/06 02:47:40 fdh + * Added prototypes for romhead.c routines. + * + * Revision 1.6 1995/02/05 01:53:05 fdh + * Modified the definition for the ROM header. + * Added a MACRO that can be used to access the + * ROM header checksum which can be in different location + * for different versions of the header. + * + * Revision 1.5 1995/02/02 20:05:31 fdh + * Moved fwid_array[] initialization to header file. + * + * Revision 1.4 1995/01/31 23:44:00 fdh + * Added field for "OPTIONAL FW ID, continued" to make + * the optional field really 7 bytes. + * + * Revision 1.3 1995/01/31 23:21:25 fdh + * Updated... + * + * Revision 1.2 1995/01/23 22:34:32 fdh + * Extended the ROM header spec. This is now version one + * which is a super-set of the version 0 header. + * + * Revision 1.1 1994/11/19 03:47:29 fdh + * Initial revision + * + * + * + * Special ROM header + * ================== + * The System ROM can contain multiple ROM images, each with + * its own header. That header tells the SROM where to load + * the image and also if it has been compressed with the + * "makerom" tool. For System ROMs which contain a single + * image, the header is optional. If the header does not + * exist the complete System ROM is loaded and executed at + * physical address zero. + * + * 31 0 + * +---------------------------------------------+ + * | VALIDATION PATTERN 0x5A5AC3C3 | 0x00 + * +---------------------------------------------+ + * | INVERSE VALIDATION PATTERN 0xA5A53C3C | 0x04 + * +---------------------------------------------+ + * | HEADER SIZE (Bytes) | 0x08 + * +---------------------------------------------+ + * | IMAGE CHECKSUM | 0x0C + * +---------------------------------------------+ + * | IMAGE SIZE (Memory Footprint) | 0x10 + * +---------------------------------------------+ + * | DECOMPRESSION FLAG | 0x14 + * +---------------------------------------------+ + * | DESTINATION ADDRESS LOWER LONGWORD | 0x18 + * +---------------------------------------------+ + * | DESTINATION ADDRESS UPPER LONGWORD | 0x1C + * +---------------------------------------------+ + * | RSVD<31:16>| ID <15:8>| HEADER REV <7:0> | 0x20 \ + * +---------------------------------------------+ \ + * | ROM IMAGE SIZE | 0x24 | + * +---------------------------------------------+ | New for + * | OPTIONAL FIRMWARE ID <31:0> | 0x28 +- Rev 1 + * +---------------------------------------------+ | headers. + * | OPTIONAL FIRMWARE ID <63:32> | 0x2C | + * +---------------------------------------------+ / + * | HEADER CHECKSUM (excluding this field) | 0x30 / + * +---------------------------------------------+ + * + * VALIDATION PATTERN + * ------------------ + * The first quadword contains a special signature pattern + * that is used to verify that this "special" ROM header + * has been located. The pattern is 0x5A5AC3C3A5A53C3C. + * + * HEADER SIZE (Bytes) + * ------------------- + * The header size is the next longword. This is provided + * to allow for some backward compatibility in the event that + * the header is extended in the future. When the header + * is located, current versions of SROM code determine where + * the image begins based on the header size. Additional data + * added to the header in the future will simply be ignored + * by current SROM code. Additionally, the header size = 0x20 + * implies version 0 of this header spec. For any other size + * see HEADER REVISION to determine header version. + * + * + * IMAGE CHECKSUM + * -------------- + * The next longword contains the image checksum. This is + * used to verify the integrity of the ROM. Checksum is computed + * in the same fashion as the header checksum. + * + * IMAGE SIZE (Memory Footprint) + * ----------------------------- + * The image size reflects the size of the image after it has + * been loaded into memory from the ROM. See ROM IMAGE SIZE. + * + * DECOMPRESSION FLAG + * ------------------ + * The decompression flag tells the SROM code if the makerom + * tool was used to compress the ROM image with a "trivial + * repeating byte algorithm". The SROM code contains routines + * which perform this decompression algorithm. Other + * compression/decompression schemes may be employed which work + * independently from this one. + * + * DESTINATION ADDRESS + * ------------------- + * This quadword contains the destination address for the + * image. The SROM code will begin loading the image at this + * address and subsequently begin its execution there. + * + * HEADER REV + * ---------- + * The revision of the header specifications used in this + * header. This is necessary to provide compatibility to + * future changes to this header spec. Version 0 headers + * are identified by the size of the header. See HEADER + * SIZE. + * + * FIRMWARE ID + * ----------- + * The firmware ID is a byte that specifies the firmware type. + * This facilitates image boot options necessary to boot + * different operating systems. + * + * firmware + * firmware type + * -------- -------- + * DBM 0 Alpha Evaluation Boards Debug Monitor + * WNT 1 Windows NT Firmware + * SRM 2 Alpha System Reference Manual Console + * + * ROM IMAGE SIZE + * -------------- + * The ROM image size reflects the size of the image as it is + * contained in the ROM. See IMAGE SIZE. + * + * OPTIONAL FW ID + * -------------- + * This is an optional field that can be used to provide + * additional firmware information such as firmware revision + * or a character descriptive string up to 8 characters. + * + * HEADER CHECKSUM + * --------------- + * The checksum of the header. This is used to validate + * the presence of a header beyond the validation provided + * by the validation pattern. See VALIDATION PATTERN. + * The header checksum is computed from the beginning of + * the header up to but excluding the header checksum + * field itself. If there are future versions of this + * header the header checksum should always be the last + * field defined in the header. The checksum algorithm used + * is compatible with the standard BSD4.3 algorithm provided + * on most implementations of Unix. Algorithm: The checksum + * is rotated right by one bit around a 16 bit field before + * adding in the value of each byte. + * + */ + +#include "local.h" /* Include environment specific definitions */ + +#define ROM_H_SIGNATURE 0x5A5AC3C3 +#define ROM_H_REVISION 1 + + +typedef union { + struct { + /* + * Version 0 definition of the ROM header. + */ + struct { + ui signature; /* validation signature */ + ui csignature; /* inverse validation signature */ + ui hsize; /* header size */ + ui checksum; /* checksum */ + ui size; /* image size (Memory Footprint) */ + ui decomp; /* decompression algorithm */ + struct { + ui low; + ui high; + } destination; /* destination address */ + } V0; + + /* + * Version 1 extensions to the ROM header. + */ + struct { + char hversion; /* ROM header version (Byte 0) */ + char fw_id; /* Firmware ID (Byte 1) */ + char reserved[2]; /* Reserved (Bytes 3:2) */ + ui rimage_size; /* ROM image size */ + union { + char id[8]; /* Optional Firmware ID (character array) */ + struct { + ui low; + ui high; + } id_S; + } fwoptid; + } V1; + + /* + * Future extensions to the header should be included before + * this header checksum. (See HEADER CHECKSUM description) + */ + ui hchecksum; /* Header checksum, (Always last entry) */ + } romh; + ui romh_array[1]; /* To allow longword access to the data */ +} romheader_t; + +/* + * Registered Firmware types. + */ +#define FW_DBM 0 +#define FW_WNT 1 +#define FW_SRM 2 + +#define FW_DBM_STRINGS "Alpha Evaluation Board Debug Monitor", "DBM", "Debug Monitor", "Monitor", NULL +#define FW_WNT_STRINGS "Windows NT Firmware", "WNT", "NTFW", "ARC", "NT", NULL +#define FW_SRM_STRINGS "Alpha SRM Console", "SRM", "VMS", "OSF", NULL + +typedef struct fw_id { + int firmware_id; + char **id_string; +} fw_id_t; + +extern fw_id_t fwid_array[]; + +#define FW_OSTYPE_DBM 0 +#define FW_OSTYPE_WNT 1 +#define FW_OSTYPE_VMS 2 +#define FW_OSTYPE_OSF 3 + +#define OS_DBM_STRINGS "Alpha Evaluation Board Debug Monitor", "DBM" +#define OS_WNT_STRINGS "The Windows NT Operating System", "NT" +#define OS_VMS_STRINGS "OpenVMS", "VMS" +#define OS_OSF_STRINGS "DEC OSF/1", "OSF" + +typedef struct os_types { + int ostype; + int firmware_id; + char **id_string; +} ostype_t; + +extern ostype_t ostype_array[]; + +/* + * The ROM header checksum should always be assigned to the last + * field in the header. Therefore, when reading headers created + * by various versions of makerom the ROM header checksum can be + * in different locations. This macro can be used to access the + * ROM header checksum in the proper location. + */ +#define ROM_HEADER_CHECKSUM(x) \ + ((x)->romh_array[((x)->romh.V0.hsize - sizeof((x)->romh.hchecksum))/sizeof(ui)]) + +/* + * Macro to provide the header version number + */ +#define ROMH_VERSION(x) ((x)->romh.V0.hsize == 0x20 ? 0 : (x)->romh.V1.hversion) + +/* + * Macro to assist in computing the BSD4.3 style checksum. + */ +#define ROTATE_RIGHT(x) if ((x) & 1) (x) = ((x) >>1) + 0x8000; else (x) = (x) >>1; + +/* + * Macro used to increment the checksum + * by a new byte while keeping the total + * checksum within the 16 bit range. + */ +#define COMPUTE_CHECKSUM(c,k) \ + {ROTATE_RIGHT(k); k += (ub) c; k &= 0xffff;} + +/* + * romheader.c prototypes + */ +extern fw_id_t * fwid_match(char * arg); +extern fw_id_t * fwid_match_i(int fwid); +extern void fwid_dump(char * pre); +extern ostype_t * ostype_match(char * arg); +extern ostype_t * ostype_match_i(int ostype); +extern void ostype_dump(char * pre); +extern ui compute_romh_chksum(romheader_t * header); +extern int dumpHeader(romheader_t * header); + +#endif /* __ROMHEAD_H_LOADED */ diff --git a/util/alpha-common/include/syms.h b/util/alpha-common/include/syms.h new file mode 100644 index 0000000000..1fabb70de3 --- /dev/null +++ b/util/alpha-common/include/syms.h @@ -0,0 +1,640 @@ +/* + * Mach Operating System + * Copyright (c) 1992 Carnegie Mellon University + * All Rights Reserved. + * + * Permission to use, copy, modify and distribute this software and its + * documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR + * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie Mellon + * the rights to redistribute these changes. + */ +/* + * HISTORY + * 31-May-92 Alessandro Forin (af) at Carnegie-Mellon University + * Adapted for Alpha. + * + * $Log$ + * Revision 1.1 2001/03/22 21:26:32 rminnich + * testing I HATE CVS + * + * Revision 1.1 2000/03/21 03:56:31 stepan + * Check in current version which is a nearly a 2.2-16 + * + * Revision 4.0 1993/10/18 15:37:42 rusling + * Include file. + * + * Revision 4.0 1993/10/18 14:39:10 rusling + * *** empty log message *** + * + * + */ +/* --------------------------------------------------- */ +/* | Copyright (c) 1986 MIPS Computer Systems, Inc. | */ +/* | All Rights Reserved. | */ +/* --------------------------------------------------- */ + +/* (C) Copyright 1984 by Third Eye Software, Inc. + * + * Third Eye Software, Inc. grants reproduction and use rights to + * all parties, PROVIDED that this comment is maintained in the copy. + * + * Third Eye makes no claims about the applicability of this + * symbol table to a particular use. + */ + +/* glevels for field in FDR */ +#define GLEVEL_0 2 +#define GLEVEL_1 1 +#define GLEVEL_2 0 /* for upward compat reasons. */ +#define GLEVEL_3 3 + +/* magic number for symheader */ +#define magicSym 0x1992 + +/* Language codes */ +#define langC 0 +#define langPascal 1 +#define langFortran 2 +#define langAssembler 3 /* one Assembley inst might map to many mach */ +#define langMachine 4 +#define langNil 5 +#define langAda 6 +#define langPl1 7 +#define langCobol 8 +#define langMax 32 + +/* The following are value definitions for the fields in the SYMR */ + +/* + * Storage Classes + */ + +#define scNil 0 +#define scText 1 /* text symbol */ +#define scData 2 /* initialized data symbol */ +#define scBss 3 /* un-initialized data symbol */ +#define scRegister 4 /* value of symbol is register number */ +#define scAbs 5 /* value of symbol is absolute */ +#define scUndefined 6 /* who knows? */ +#define scCdbLocal 7 /* variable's value is IN se->va.?? */ +#define scBits 8 /* this is a bit field */ +#define scCdbSystem 9 /* variable's value is IN CDB's address space */ +#define scDbx 9 /* overlap dbx internal use */ +#define scRegImage 10 /* register value saved on stack */ +#define scInfo 11 /* symbol contains debugger information */ +#define scUserStruct 12 /* address in struct user for current process */ +#define scSData 13 /* load time only small data */ +#define scSBss 14 /* load time only small common */ +#define scRData 15 /* load time only read only data */ +#define scVar 16 /* Var parameter (fortran,pascal) */ +#define scCommon 17 /* common variable */ +#define scSCommon 18 /* small common */ +#define scVarRegister 19 /* Var parameter in a register */ +#define scVariant 20 /* Variant record */ +#define scSUndefined 21 /* small undefined(external) data */ +#define scInit 22 /* .init section symbol */ +#define scBasedVar 23 /* Fortran or PL/1 ptr based var */ +#define scXData 24 /* exception handling data */ +#define scPData 25 /* Procedure section */ +#define scFini 26 /* .fini section */ +#define scMax 32 + + +/* + * Symbol Types + */ + +#define stNil 0 /* Nuthin' special */ +#define stGlobal 1 /* external symbol */ +#define stStatic 2 /* static */ +#define stParam 3 /* procedure argument */ +#define stLocal 4 /* local variable */ +#define stLabel 5 /* label */ +#define stProc 6 /* " " Procedure */ +#define stBlock 7 /* beginnning of block */ +#define stEnd 8 /* end (of anything) */ +#define stMember 9 /* member (of anything - struct/union/enum */ +#define stTypedef 10 /* type definition */ +#define stFile 11 /* file name */ +#define stRegReloc 12 /* register relocation */ +#define stForward 13 /* forwarding address */ +#define stStaticProc 14 /* load time only static procs */ +#define stConstant 15 /* const */ +#define stStaParam 16 /* Fortran static parameters */ + /* Psuedo-symbols - internal to debugger */ +#define stStr 60 /* string */ +#define stNumber 61 /* pure number (ie. 4 NOR 2+2) */ +#define stExpr 62 /* 2+2 vs. 4 */ +#define stType 63 /* post-coersion SER */ +#define stMax 64 + +/* definitions for fields in TIR */ + +/* type qualifiers for ti.tq0 -> ti.(itqMax-1) */ +#define tqNil 0 /* bt is what you see */ +#define tqPtr 1 /* pointer */ +#define tqProc 2 /* procedure */ +#define tqArray 3 /* duh */ +#define tqFar 4 /* longer addressing - 8086/8 land */ +#define tqVol 5 /* volatile */ +#define tqConst 6 /* const */ +#define tqMax 8 + +/* basic types as seen in ti.bt */ +#define btNil 0 /* undefined */ +#define btAdr32 1 /* 32-bit address */ +#define btAdr btAdr32 /* address - integer same size as pointer */ +#define btChar 2 /* character */ +#define btUChar 3 /* unsigned character */ +#define btShort 4 /* short */ +#define btUShort 5 /* unsigned short */ +#define btInt32 6 /* 32-bit int */ +#define btInt btInt32 /* int */ +#define btUInt32 7 /* 32-bit unsigned int */ +#define btUInt btUInt32 /* unsigned int */ +#define btLong32 8 /* 32-bit long */ +#define btLong btLong32 /* long */ +#define btULong32 9 /* 32-bit unsigned long */ +#define btULong btULong32 /* unsigned long */ +#define btFloat 10 /* float (real) */ +#define btDouble 11 /* Double (real) */ +#define btStruct 12 /* Structure (Record) */ +#define btUnion 13 /* Union (variant) */ +#define btEnum 14 /* Enumerated */ +#define btTypedef 15 /* defined via a typedef, isymRef points */ +#define btRange 16 /* subrange of int */ +#define btSet 17 /* pascal sets */ +#define btComplex 18 /* fortran complex */ +#define btDComplex 19 /* fortran double complex */ +#define btIndirect 20 /* forward or unnamed typedef */ +#define btFixedDec 21 /* Fixed Decimal */ +#define btFloatDec 22 /* Float Decimal */ +#define btString 23 /* Varying Length Character String */ +#define btBit 24 /* Aligned Bit String */ +#define btPicture 25 /* Picture */ +#define btVoid 26 /* void */ +#define btPtrMem 27 /* DEC C++: Pointer to member */ +#define btInt64 28 /* 64-bit int */ +#define btUInt64 29 /* 64-bit unsigned int */ +#define btLong64 30 /* 64-bit long */ +#define btULong64 31 /* 64-bit unsigned long */ +#define btLongLong64 32 /* 64-bit long long */ +#define btLongLong btLongLong64 /* long long */ +#define btULongLong64 33 /* 64-bit unsigned long long */ +#define btULongLong btULongLong64 /* unsigned long long */ +#define btAdr64 34 /* 64-bit address */ +#define btMax 64 + +#if (MFG == MIPS) +/* optimization type codes */ +#define otNil 0 +#define otReg 1 /* move var to reg */ +#define otBlock 2 /* begin basic block */ +#define otProc 3 /* procedure */ +#define otInline 4 /* inline procedure */ +#define otEnd 5 /* whatever you started */ +#define otMax 6 /* KEEP UP TO DATE */ +#endif (MFG == MIPS) + + +#ifdef LANGUAGE_C + +/* + * This (part of the) file contains the definition of the Third Eye Symbol Table. + * + * Symbols are assumed to be in 'encounter order' - i.e. the order that + * the things they represent were encountered by the compiler/assembler/loader. + * EXCEPT for globals! These are assumed to be bunched together, + * probably right after the last 'normal' symbol. Globals ARE sorted + * in ascending order. + * + * ----------------------------------------------------------------- + * A brief word about Third Eye naming/use conventions: + * + * All arrays and index's are 0 based. + * All "ifooMax" values are the highest legal value PLUS ONE. This makes + * them good for allocating arrays, etc. All checks are "ifoo < ifooMax". + * + * "isym" Index into the SYMbol table. + * "ipd" Index into the Procedure Descriptor array. + * "ifd" Index into the File Descriptor array. + * "iss" Index into String Space. + * "cb" Count of Bytes. + * "rgPd" array whose domain is "0..ipdMax-1" and RanGe is PDR. + * "rgFd" array whose domain is "0..ifdMax-1" and RanGe is FDR. + */ + + +/* + * Symbolic Header (HDR) structure. + * As long as all the pointers are set correctly, + * we don't care WHAT order the various sections come out in! + * + * A file produced solely for the use of CDB will probably NOT have + * any instructions or data areas in it, as these are available + * in the original. + */ + +typedef struct { + short magic; /* to verify validity of the table */ + short vstamp; /* version stamp */ + int ilineMax; /* number of line number entries */ + int idnMax; /* max index into dense number table */ + int ipdMax; /* number of procedures */ + int isymMax; /* number of local symbols */ + int ioptMax; /* max index into optimization symbol entries */ + int iauxMax; /* number of auxillary symbol entries */ + int issMax; /* max index into local strings */ + int issExtMax; /* max index into external strings */ + int ifdMax; /* number of file descriptor entries */ + int crfd; /* number of relative file descriptor entries */ + int iextMax; /* max index into external symbols */ + unsigned long cbLine; /* number of bytes for line number entries */ + unsigned long cbLineOffset;/* offset to start of line number entries*/ + unsigned long cbDnOffset;/* offset to start dense number table */ + unsigned long cbPdOffset;/* offset to procedure descriptor table */ + unsigned long cbSymOffset;/* offset to start of local symbols*/ + unsigned long cbOptOffset;/* offset to optimization symbol entries */ + unsigned long cbAuxOffset;/* offset to start of auxillary symbol entries*/ + unsigned long cbSsOffset;/* offset to start of local strings */ + unsigned long cbSsExtOffset;/* offset to start of external strings */ + unsigned long cbFdOffset;/* offset to file descriptor table */ + unsigned long cbRfdOffset;/* offset to relative file descriptor table */ + unsigned long cbExtOffset;/* offset to start of external symbol entries*/ + /* If you add machine dependent fields, add them here */ + } HDRR, *pHDRR; +#define cbHDRR sizeof(HDRR) +#define hdrNil ((pHDRR)0) + +/* + * The FDR and PDR structures speed mapping of address <-> name. + * They are sorted in ascending memory order and are kept in + * memory by CDB at runtime. + */ + +/* + * File Descriptor + * + * There is one of these for EVERY FILE, whether compiled with + * full debugging symbols or not. The name of a file should be + * the path name given to the compiler. This allows the user + * to simply specify the names of the directories where the COMPILES + * were done, and we will be able to find their files. + * A field whose comment starts with "R - " indicates that it will be + * setup at runtime. + */ +typedef struct fdr { + unsigned long adr; /* memory address of beginning of file */ + unsigned long cbLineOffset;/* byte offset from header for this file ln's */ + unsigned long cbLine; /* size of lines for this file */ + unsigned long cbSs; /* number of bytes in the ss */ + int rss; /* file name (of source, if known) */ + int issBase; /* file's string space */ + int isymBase; /* beginning of symbols */ + int csym; /* count file's of symbols */ + int ilineBase; /* file's line symbols */ + int cline; /* count of file's line symbols */ + int ioptBase; /* file's optimization entries */ + int copt; /* count of file's optimization entries */ + int ipdFirst; /* start of procedures for this file */ + int cpd; /* count of procedures for this file */ + int iauxBase; /* file's auxiliary entries */ + int caux; /* count of file's auxiliary entries */ + int rfdBase; /* index into the file indirect table */ + int crfd; /* count file indirect entries */ + unsigned lang: 5; /* language for this file */ + unsigned fMerge : 1; /* whether this file can be merged */ + unsigned fReadin : 1; /* true if it was read in (not just created) */ + unsigned fBigendian : 1;/* if set, was compiled on big endian machine */ + /* aux's will be in compile host's sex */ + unsigned glevel : 2; /* level this file was compiled with */ + unsigned reserved : 22; /* reserved for future use */ + } FDR, *pFDR; +#define cbFDR sizeof(FDR) +#define fdNil ((pFDR)0) +#define ifdNil -1 +#define ifdTemp 0 +#define ilnNil -1 + + +/* + * Procedure Descriptor + * + * There is one of these for EVERY TEXT LABEL. + * If a procedure is in a file with full symbols, then isym + * will point to the PROC symbols, else it will point to the + * global symbol for the label. + */ + +typedef struct pdr { + unsigned long adr; /* memory address of start of procedure */ + unsigned long cbLineOffset;/* byte offset for this procedure from the fd base */ + int isym; /* start of local symbol entries */ + int iline; /* start of line number entries*/ + int regmask; /* save register mask */ + int regoffset; /* save register offset */ + int iopt; /* start of optimization symbol entries*/ + int fregmask; /* save floating point register mask */ + int fregoffset; /* save floating point register offset */ + int frameoffset; /* frame size */ + int lnLow; /* lowest line in the procedure */ + int lnHigh; /* highest line in the procedure */ + unsigned gp_prologue : 8; /* byte size of GP prologue */ + unsigned gp_used : 1; /* true if the procedure uses GP */ + unsigned reserved : 23; + short framereg; /* frame pointer register */ + short pcreg; /* offset or reg of return pc */ + } PDR, *pPDR; +#define cbPDR sizeof(PDR) +#define pdNil ((pPDR) 0) +#define ipdNil -1 + +/* + * The structure of the runtime procedure descriptor created by the loader + * for use by the static exception system. + */ +typedef struct runtime_pdr { + unsigned long adr; /* memory address of start of procedure */ + int regmask; /* save register mask */ + int regoffset; /* save register offset */ + int fregmask; /* save floating point register mask */ + int fregoffset; /* save floating point register offset */ + int frameoffset; /* frame size */ + short framereg; /* frame pointer register */ + short pcreg; /* offset or reg of return pc */ + int irpss; /* index into the runtime string table */ + int reserved; + struct exception_info *exception_info;/* pointer to exception array */ +} RPDR, *pRPDR; +#define cbRPDR sizeof(RPDR) +#define rpdNil ((pRPDR) 0) + +/* + * Line Numbers + * + * Line Numbers are segregated from the normal symbols because they + * are [1] smaller , [2] are of no interest to your + * average loader, and [3] are never needed in the middle of normal + * scanning and therefore slow things down. + * + * By definition, the first LINER for any given procedure will have + * the first line of a procedure and represent the first address. + */ + +typedef int LINER, *pLINER; +#define lineNil ((pLINER)0) +#define cbLINER sizeof(LINER) +#define ilineNil -1 + + + +/* + * The Symbol Structure (GFW, to those who Know!) + */ + +typedef struct { + unsigned long value; /* value of symbol */ + int iss; /* index into String Space of name */ + unsigned st : 6; /* symbol type */ + unsigned sc : 5; /* storage class - text, data, etc */ + unsigned reserved : 1; /* reserved */ + unsigned index : 20; /* index into sym/aux table */ + } SYMR, *pSYMR; +#define symNil ((pSYMR)0) +#define cbSYMR sizeof(SYMR) +#define isymNil -1 +#define indexNil 0xfffff +#define issNil -1 +#define issNull 0 + + +/* The following converts a memory resident string to an iss. + * This hack is recognized in SbFIss, in sym.c of the debugger. + */ +#define IssFSb(sb) (0x80000000 | ((unsigned int)(sb))) + +/* E X T E R N A L S Y M B O L R E C O R D + * + * Same as the SYMR except it contains file context to determine where + * the index is. + */ +typedef struct { + SYMR asym; /* symbol for the external */ + unsigned jmptbl:1; /* symbol is a jump table entry for shlibs */ + unsigned cobol_main:1; /* symbol is a cobol main procedure */ + unsigned weakext:1; /* symbol is weak external */ + unsigned reserved:29; /* reserved for future use */ + int ifd; /* where the iss and index fields point into */ + } EXTR, *pEXTR; +#define extNil ((pEXTR)0) +#define cbEXTR sizeof(EXTR) + + +/* A U X I L L A R Y T Y P E I N F O R M A T I O N */ + +/* + * Type Information Record + */ +typedef struct { + unsigned fBitfield : 1; /* set if bit width is specified */ + unsigned continued : 1; /* indicates additional TQ info in next AUX */ + unsigned bt : 6; /* basic type */ + unsigned tq4 : 4; + unsigned tq5 : 4; + /* ---- 16 bit boundary ---- */ + unsigned tq0 : 4; + unsigned tq1 : 4; /* 6 type qualifiers - tqPtr, etc. */ + unsigned tq2 : 4; + unsigned tq3 : 4; + } TIR, *pTIR; +#define cbTIR sizeof(TIR) +#define tiNil ((pTIR)0) +#define itqMax 6 + +/* + * Relative symbol record + * + * If the rfd field is 4095, the index field indexes into the global symbol + * table. + */ + +typedef struct { + unsigned rfd : 12; /* index into the file indirect table */ + unsigned index : 20; /* index int sym/aux/iss tables */ + } RNDXR, *pRNDXR; +#define cbRNDXR sizeof(RNDXR) +#define rndxNil ((pRNDXR)0) + +/* dense numbers or sometimes called block numbers are stored in this type, + * a rfd of 0xffffffff is an index into the global table. + */ +typedef struct { + unsigned int rfd; /* index into the file table */ + unsigned int index; /* index int sym/aux/iss tables */ + } DNR, *pDNR; +#define cbDNR sizeof(DNR) +#define dnNil ((pDNR)0) + + + +/* + * Auxillary information occurs only if needed. + * It ALWAYS occurs in this order when present. + + isymMac used by stProc only + TIR type info + TIR additional TQ info (if first TIR was not enough) + rndx if (bt == btStruct,btUnion,btEnum,btSet,btRange, + btTypedef): + rsym.index == iaux for btSet or btRange + else rsym.index == isym + dimLow btRange, btSet + dimMac btRange, btSet + rndx0 As many as there are tq arrays + dimLow0 + dimHigh0 + ... + rndxMax-1 + dimLowMax-1 + dimHighMax-1 + width in bits if (bit field), width in bits. + */ +#define cAuxMax (6 + (idimMax*3)) + +/* a union of all possible info in the AUX universe */ +typedef union { + TIR ti; /* type information record */ + RNDXR rndx; /* relative index into symbol table */ + int dnLow; /* low dimension */ + int dnHigh; /* high dimension */ + int isym; /* symbol table index (end of proc) */ + int iss; /* index into string space (not used) */ + int width; /* width for non-default sized struc fields */ + int count; /* count of ranges for variant arm */ + } AUXU, *pAUXU; +#define cbAUXU sizeof(AUXU) +#define auxNil ((pAUXU)0) +#define iauxNil -1 + + +/* + * Optimization symbols + * + * Optimization symbols contain some overlap information with the normal + * symbol table. In particular, the proc information + * is somewhat redundant but necessary to easily find the other information + * present. + * + * All of the offsets are relative to the beginning of the last otProc + */ + +typedef struct { + unsigned ot: 8; /* optimization type */ + unsigned value: 24; /* address where we are moving it to */ + RNDXR rndx; /* points to a symbol or opt entry */ + unsigned int offset; /* relative offset this occured */ + } OPTR, *pOPTR; +#define optNil ((pOPTR) 0) +#define cbOPTR sizeof(OPTR) +#define ioptNil -1 + +/* + * File Indirect + * + * When a symbol is referenced across files the following procedure is used: + * 1) use the file index to get the File indirect entry. + * 2) use the file indirect entry to get the File descriptor. + * 3) add the sym index to the base of that file's sym table + * + */ + +typedef int RFDT, *pRFDT; +#define cbRFDT sizeof(RFDT) +#define rfdNil -1 + +/* + * The file indirect table in the mips loader is known as an array of FITs. + * This is done to keep the code in the loader readable in the area where + * these tables are merged. Note this is only a name change. + */ +typedef int FIT, *pFIT; +#define cbFIT sizeof(FIT) +#define ifiNil -1 +#define fiNil ((pFIT) 0) + + +/* Dense numbers + * + * Rather than use file index, symbol index pairs to represent symbols + * and globals, we use dense number so that they can be easily embeded + * in intermediate code and the programs that process them can + * use direct access tabls instead of hash table (which would be + * necesary otherwise because of the sparse name space caused by + * file index, symbol index pairs. Dense number are represented + * by RNDXRs. + */ + +/* + * The following table defines the meaning of each SYM field as + * a function of the "st". (scD/B == scData OR scBss) + * + * Note: the value "isymMac" is used by symbols that have the concept + * of enclosing a block of related information. This value is the + * isym of the first symbol AFTER the end associated with the primary + * symbol. For example if a procedure was at isym==90 and had an + * isymMac==155, the associated end would be at isym==154, and the + * symbol at 155 would probably (although not necessarily) be the + * symbol for the next procedure. This allows rapid skipping over + * internal information of various sorts. "stEnd"s ALWAYS have the + * isym of the primary symbol that started the block. + * + +ST SC VALUE INDEX +-------- ------ -------- ------ +stFile scText address isymMac +stLabel scText address --- +stGlobal scD/B address iaux +stStatic scD/B address iaux +stParam scAbs offset iaux +stLocal scAbs offset iaux +stProc scText address iaux (isymMac is first AUX) +stStaticProc scText address iaux (isymMac is first AUX) + +stMember scNil ordinal --- (if member of enum) +stMember scNil byte offset iaux (if member of struct/union) +stMember scBits bit offset iaux (bit field spec) + +stBlock scText address isymMac (text block) +stBlock scNil cb isymMac (struct/union member define) +stBlock scNil cMembers isymMac (enum member define) + +stEnd scText address isymStart +stEnd scNil ------- isymStart (struct/union/enum) + +stTypedef scNil ------- iaux +stRegReloc sc??? value old register number +stForward sc??? new address isym to original symbol + +stConstant scInfo value --- (scalar) +stConstant scInfo iss --- (complex, e.g. string) + + * + */ + +#endif LANGUAGE_C + diff --git a/util/alpha-common/romhead.c b/util/alpha-common/romhead.c new file mode 100644 index 0000000000..023d30dc9d --- /dev/null +++ b/util/alpha-common/romhead.c @@ -0,0 +1,288 @@ + +/***************************************************************************** + + Copyright © 1993, 1994 Digital Equipment Corporation, + Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, provided +that the copyright notice and this permission notice appear in all copies +of software and supporting documentation, and that the name of Digital not +be used in advertising or publicity pertaining to distribution of the software +without specific, written prior permission. Digital grants this permission +provided that you prominently mark, as not part of the original, any +modifications made to this software or documentation. + +Digital Equipment Corporation disclaims all warranties and/or guarantees +with regard to this software, including all implied warranties of fitness for +a particular purpose and merchantability, and makes no representations +regarding the use of, or the results of the use of, the software and +documentation in terms of correctness, accuracy, reliability, currentness or +otherwise; and you rely on the software, documentation and results solely at +your own risk. + +******************************************************************************/ + +#ifndef LINT +static char *rcsid = "$Id$"; +#endif + +/* + * $Log$ + * Revision 1.1 2001/03/22 21:26:32 rminnich + * testing I HATE CVS + * + * Revision 1.1 2000/03/21 03:56:31 stepan + * Check in current version which is a nearly a 2.2-16 + * + * Revision 1.13 1995/02/27 19:22:33 fdh + * Print header->romh.V0.destination as two longwords instead of + * a single quadword. + * + * Revision 1.12 1995/02/27 15:35:26 fdh + * Modified to not use 64 bit ints for portability. + * + * Revision 1.11 1995/02/25 05:18:13 fdh + * Print 64bit fields as type long. + * + * Revision 1.10 1995/02/19 17:47:31 fdh + * Modified an error message. + * + * Revision 1.9 1995/02/16 20:46:31 fdh + * Print out decimal representation of image checksum too. + * + * Revision 1.8 1995/02/10 19:08:55 fdh + * Minor fixup. + * + * Revision 1.7 1995/02/10 02:18:11 fdh + * Moved compute_romh_chksum() to this file. + * + * Revision 1.5 1995/02/07 04:57:30 fdh + * Modified fwid_match_i(). + * Added ostype_array[] and routines for accessing it. + * + * Revision 1.4 1995/02/07 01:04:05 fdh + * Removed some unnecessary definitions. + * + * Revision 1.3 1995/02/06 02:44:42 fdh + * Added fwid_match(), fwid_match_i(), and fwid_dump() routines. + * + * Revision 1.2 1995/02/05 01:59:05 fdh + * Added include files and definitions. + * + * Revision 1.1 1995/02/03 16:35:37 fdh + * Initial revision + * + */ + +#include +#include "romhead.h" + +char *fw_dbm_id[] = {FW_DBM_STRINGS}; +char *fw_wnt_id[] = {FW_WNT_STRINGS}; +char *fw_srm_id[] = {FW_SRM_STRINGS}; + +fw_id_t fwid_array[] = { + { FW_DBM, fw_dbm_id}, + { FW_WNT, fw_wnt_id}, + { FW_SRM, fw_srm_id}, + { 0, NULL} +}; + +char *ostype_dbm[] = {OS_DBM_STRINGS}; +char *ostype_wnt[] = {OS_WNT_STRINGS}; +char *ostype_vms[] = {OS_VMS_STRINGS}; +char *ostype_osf[] = {OS_OSF_STRINGS}; + +ostype_t ostype_array[] = { + { FW_OSTYPE_DBM, FW_DBM, ostype_dbm}, + { FW_OSTYPE_WNT, FW_WNT, ostype_wnt}, + { FW_OSTYPE_VMS, FW_SRM, ostype_vms}, + { FW_OSTYPE_OSF, FW_SRM, ostype_osf}, + { 0, 0, NULL} +}; + +#define MAXSTRING 80 +char strbuf1[MAXSTRING+1]; +char strbuf2[MAXSTRING+1]; + +fw_id_t *fwid_match(char *arg) +{ + fw_id_t *ptr; + int i, k; + + ptr = fwid_array; + strncpy(strbuf1, arg, MAXSTRING); + strbuf1[MAXSTRING+1] = '\0'; + k = 0; + while ((strbuf1[k] = tolower(strbuf1[k])) != '\0') ++k; + + while (ptr->id_string) { + i = 0; + while (ptr->id_string[i]) { + strncpy(strbuf2, ptr->id_string[i], MAXSTRING); + strbuf2[MAXSTRING+1] = '\0'; + k = 0; + while ((strbuf2[k] = tolower(strbuf2[k])) != '\0') ++k; + + if (strcmp(strbuf1, strbuf2) == 0) + return (ptr); + + ++i; + } + ++ptr; + } + return ((fw_id_t *)NULL); +} + +fw_id_t *fwid_match_i(int fwid) +{ + fw_id_t *ptr; + + ptr = fwid_array; + while (ptr->id_string) { + if (fwid == ptr->firmware_id) + return (ptr); + + ++ptr; + } + return ((fw_id_t *)NULL); +} + +void fwid_dump(char *pre) +{ + fw_id_t *ptr; + int i; + + ptr = fwid_array; + while (ptr->id_string) { + i = 0; + printf("%s\"%d\"", pre, ptr->firmware_id); + while (ptr->id_string[i]) + printf(" \"%s\"", ptr->id_string[i++]); + printf("\n"); + ++ptr; + } +} + +ostype_t *ostype_match(char *arg) +{ + ostype_t *ptr; + int i, k; + + ptr = ostype_array; + strncpy(strbuf1, arg, MAXSTRING); + strbuf1[MAXSTRING+1] = '\0'; + k = 0; + while ((strbuf1[k] = tolower(strbuf1[k])) != '\0') ++k; + + while (ptr->id_string) { + for (i=0; i<2; ++i) { + strncpy(strbuf2, ptr->id_string[i], MAXSTRING); + strbuf2[MAXSTRING+1] = '\0'; + k = 0; + while ((strbuf2[k] = tolower(strbuf2[k])) != '\0') ++k; + + if (strcmp(strbuf1, strbuf2) == 0) + return (ptr); + } + ++ptr; + } + return ((ostype_t *)NULL); +} + +ostype_t *ostype_match_i(int ostype) +{ + ostype_t *ptr; + + ptr = ostype_array; + while (ptr->id_string) { + if (ostype == ptr->ostype) + return (ptr); + ++ptr; + } + return ((ostype_t *)NULL); +} + +void ostype_dump(char *pre) +{ + ostype_t *ptr; + int i; + + ptr = ostype_array; + while (ptr->id_string) { + printf("%s\"%d\"", pre, ptr->ostype); + for (i=0; i<2; ++i) + printf(" \"%s\"", ptr->id_string[i]); + printf("\n"); + ++ptr; + } +} + +/* + * Compute the header checksum. + */ +ui compute_romh_chksum(romheader_t *header) +{ + char *ptr; + ui chksum = 0; + + ptr = (char *) header; + while (ptr < (char *) &header->romh.hchecksum) { + COMPUTE_CHECKSUM(*ptr,chksum); + ++ptr; + } + return (chksum); +} + +/* Prints out the ROM header pointed to by argument. + * Returns TRUE if header is valid; FALSE otherwise. + */ +int dumpHeader(romheader_t *header) +{ + + int i, hver; + ui hchksum; + fw_id_t *fwid_ptr; + + printf(" Header Size......... %d bytes\n", header->romh.V0.hsize); + printf(" Image Checksum...... 0x%04x (%d)\n", + header->romh.V0.checksum, header->romh.V0.checksum); + printf(" Image Size (Uncomp). %d (%d KB)\n", header->romh.V0.size, header->romh.V0.size/1024); + printf(" Compression Type.... %d\n", header->romh.V0.decomp); + printf(" Image Destination... 0x%08x%08x\n", + header->romh.V0.destination.high, + header->romh.V0.destination.low); + + if ((hver = ROMH_VERSION(header)) > 0) /* Version > 0 */ + { + printf(" Header Version...... %d\n", (ui) hver); + + fwid_ptr = fwid_match_i(header->romh.V1.fw_id); + printf(" Firmware ID......... %d - %s\n", + (ui) header->romh.V1.fw_id, + fwid_ptr == NULL ? "Unknown ID Type." : fwid_ptr->id_string[0]); + + printf(" ROM Image Size...... %d (%d KB)\n", header->romh.V1.rimage_size, + header->romh.V1.rimage_size/1024); + + printf(" Firmware ID (Opt.).. %08x%08x ", + header->romh.V1.fwoptid.id_S.high, + header->romh.V1.fwoptid.id_S.low); + for (i = 0; i < 8; i++) + if (isprint(header->romh.V1.fwoptid.id[i])) + printf ("%c", header->romh.V1.fwoptid.id[i]); + else printf ("."); + printf("\n Header Checksum..... 0x%04x", header->romh.hchecksum); + hchksum = compute_romh_chksum(header); + if (hchksum != header->romh.hchecksum) { + printf("\nERROR: Bad ROM header checksum. 0x%04x\n", hchksum); + return (FALSE); + } + else + printf ("\n"); + } + return (TRUE); +} diff --git a/util/makerom/Config b/util/makerom/Config new file mode 100644 index 0000000000..59d95f0b39 --- /dev/null +++ b/util/makerom/Config @@ -0,0 +1,9 @@ + + +makerule makerom: commlib.a makerom.o compress.o ; $(CC) -o makerom makerom.o compress.o commlib.a + +makerule makerom.o: $(TOP)/util/makerom/makerom.c ; $(CC) -c -I$(TOP)/util/alpha-common/include $(TOP)/util/makerom/makerom.c + +makerule compress.o: $(TOP)/util/makerom/compress.c ; $(CC) -c -I$(TOP)/util/alpha-common/include $(TOP)/util/makerom/compress.c + +dir /util/alpha-common diff --git a/util/makerom/Makefile b/util/makerom/Makefile new file mode 100644 index 0000000000..78619f8d76 --- /dev/null +++ b/util/makerom/Makefile @@ -0,0 +1,33 @@ +PROG = makerom +OBJS = makerom.o compress.o + +COMMON = ../common +COMMONLIB = $(COMMON)/commlib.a + +BIN = ../bin + +CC = gcc +STRIP = strip +CHMOD = chmod +RM = rm -f +CP = cp -fp + +CFLAGS = -O2 +INCLUDES = -I../include + +all: $(PROG) + +$(PROG): $(OBJS) $(COMMONLIB) + $(CC) -o $(PROG) $(OBJS) $(COMMONLIB) + $(STRIP) $(PROG) + +install: $(PROG) + $(CP) $(PROG) $(BIN) + $(CHMOD) 775 $(BIN)/$(PROG) + +clean: + $(RM) $(BIN)/$(PROG) $(PROG) *.o *~ + +.c.o: + $(CC) $(CFLAGS) $(DEFINES) $(INCLUDES) -c -o $*.o $< + diff --git a/util/makerom/compress.c b/util/makerom/compress.c new file mode 100644 index 0000000000..e6ef640705 --- /dev/null +++ b/util/makerom/compress.c @@ -0,0 +1,348 @@ +/***************************************************************************** + +Copyright © 1994, Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, provided +that the copyright notice and this permission notice appear in all copies +of software and supporting documentation, and that the name of Digital not +be used in advertising or publicity pertaining to distribution of the software +without specific, written prior permission. Digital grants this permission +provided that you prominently mark, as not part of the original, any +modifications made to this software or documentation. + +Digital Equipment Corporation disclaims all warranties and/or guarantees +with regard to this software, including all implied warranties of fitness for +a particular purpose and merchantability, and makes no representations +regarding the use of, or the results of the use of, the software and +documentation in terms of correctness, accuracy, reliability, currentness or +otherwise; and you rely on the software, documentation and results solely at +your own risk. + +******************************************************************************/ +/* +** +** FACILITY: +** +** EBxx Software Tools - makerom +** +** FUNCTIONAL DESCRIPTION: +** +** Makerom makes roms. It takes a series of input files +** adds headers to them and outputs them either compressed +** or uncompressed (the default). This module contains the +** compressioin code. +** +** CALLING ENVIRONMENT: +** +** user mode +** +** AUTHOR: David A Rusling +** +** CREATION-DATE: 04-Feb-1994 +** +** MODIFIED BY: +** +*/ +#ifndef lint +static char *RCSid = "$Id$"; +#endif + +/* + * $Log$ + * Revision 1.1 2001/03/22 21:26:32 rminnich + * testing I HATE CVS + * + * Revision 1.1 2000/03/21 03:56:31 stepan + * Check in current version which is a nearly a 2.2-16 + * + * Revision 1.9 1995/03/04 05:54:15 fdh + * Keep track of output size. + * Use the pre-defined macros for computing checksum. + * + * Revision 1.8 1995/02/08 01:22:40 fdh + * Pad to longword align the end of the ROM image. + * + * Revision 1.7 1995/02/07 01:01:12 fdh + * Removed some unnecessary definitions. + * + * Revision 1.6 1995/02/05 02:02:07 fdh + * Modified to accept the latest romheader definition. + * + * Revision 1.5 1995/02/02 20:28:03 fdh + * Wrapped _fputc() with output_c() to keep count of the + * bytes written. + * Modified to work in two passes with conditional + * output enable. + * + * Revision 1.4 1994/07/04 10:58:22 rusling + * Fixed WNT compile warnings. + * + * Revision 1.3 1994/04/19 12:37:53 rusling + * Fixed up compression message. + * + * Revision 1.2 1994/03/03 16:15:38 rusling + * Fixed bug. + * + * Revision 1.5 1994/02/04 11:51:26 rusling + * Ported to Alpha WNT. + * + * Revision 1.3 1994/02/04 11:22:35 rusling + * Fixed but (not resetting index) in push() when + * we flush some of the stack. + * + * Revision 1.2 1994/02/04 10:17:26 rusling + * Added RCS bits to the file. + * + */ + +#include +#include +#include +#include +#include "c_32_64.h" +#include "romhead.h" + +/* + * Function prototypes + */ +extern int compress(FILE * in , FILE * out); +static int pop(void); +static void flush(FILE * out); +static void push(int c , FILE * out); +static void Repeater(int c , int repeat , FILE * out); +static void output_c(int c , FILE * f); + +#define MAXDIFFERENT 127 +#define MAXREPEAT 128 +#define MINREPEAT 2 /* As when this is output as + a repeated record, then the + output is no longer than the + input */ + +#define _minimum(a,b) ((a < b)? (a) : (b)) +#define _maximum(a,b) ((a > b)? (a) : (b)) + +/* + * Global variables used by the helper routines. + */ +#define MAXBUFFER (2 * (MINREPEAT + MAXDIFFERENT)) +int buffer[MAXBUFFER]; +int idx = 0; +extern int output_enable; +extern romheader_t head; + +/* + * Global values used by statistics gatherers. + */ +int ccount; +int ocount; +int rrecords; +int nrecords; +int toosmall; +/***************************************************** + * Helper routines maintaining a stack. * + *****************************************************/ + +/* + * Pop the top charater off of the stack. + */ +static int pop() +{ + if (idx != 0) + return buffer[idx--]; + else { + fprintf(stderr, "ERROR: attempting to pop an empty stack\n"); + exit(0); + } +} + +/* + * Flush the stack out as a series of non + * repeating records of maximum size MAXDIFFERENT. + */ +static void flush(FILE *out) +{ + int i = 0, j; + + while (idx > i) { + j = 0; + output_c(_minimum(MAXDIFFERENT, idx - i), out); + while (j < _minimum(MAXDIFFERENT, idx - i)) { + output_c(buffer[i + (j++)], out); + } + nrecords++; + i = i + MAXDIFFERENT; + } + idx = 0; +} +/* + * Push a character onto the stack, if it gets full + * then flush it. The last character must be available. + * This is wy we pass in the output file stream pointer. + */ +static void push(int c, FILE *out) +{ + if (idx == MAXBUFFER) + flush(out); + + buffer[idx++] = c; +} + +/* + * Print out a series of repeater records. + */ +static void Repeater(int c, int repeat, FILE *out) +{ + int i = 0; + + while (repeat > i) { + output_c(-(_minimum(MAXREPEAT, repeat - i)), out); + output_c(c, out); + rrecords++; + i = i + MAXREPEAT; + } +} + + +int compress(FILE *in, FILE *out) +{ + int last, this; + int padding; + +#define REPEATING 1 +#define NONE 0 + int state = NONE; + int repeat = 0; + float compression; + +ccount = 0; +ocount = 0; +rrecords = 0; +nrecords = 0; +toosmall = 0; + +/* + * Read the input stream byte by byte writing + * compression records. These are either repeating records + * or non-repeating records. Finally, output an end of + * file record (0). + */ + last = getc(in); + push(last, out); + ccount++; + + this = getc(in); + while (!feof(in)) { + ccount++; + if (state == REPEATING) { +/* + * At least the last two characters were the same. If this + * one is then we're still in a run of the same character + * (which is "last"). However, if it's different, then + * we've reached the end of the repeat run. + */ + if (last == this) { + repeat++; + } else { +/* + * We've reached the end of a repeating string of character + * "last". If this repeat string is not long enough, then do + * not worry about, just stick it on the stack, otherwise + * put out whatever was before the repeated character and + * then put out a repeat record. + */ + state = NONE; + if (repeat < MINREPEAT+1) { + toosmall++; + while (repeat--) + push(last, out); + } else { + flush(out); /* flush the non-repeating record + * before we got to the repetitive + * character */ + Repeater(last, repeat, out); + /* write out the repeater record */ + repeat = 0; + } + push(this, out); + } + } else { +/* + * We're just bumbling along seeing different characters + * all the time. If we see the same character as last time, + * then we change our state to repeating and take that + * last character off of the stack. Otherwise we just + * carry on pushing characters onto the stack. When the + * stack fills, then it will be emptied as non-repeating + * records by flush(). + */ + if (last == this) { + state = REPEATING; + pop(); /* don't put repeating chars on the + * stack, we did, so take it off! */ + repeat = 2; /* this one and the last one! */ + } else { + push(this, out); + } + } + last = this; + this = getc(in); + } +/* + * Flush whatever is lying in the stack as non-repeating + * records. Then put out any repeat record. + */ + flush(out); + Repeater(last, repeat, out); +/* + * Print out the end of file record. + */ + output_c(0, out); + + /* Pad to longword align the end of the file */ + padding = 0; + while((ocount%4) != 0) { + output_c(0, out); + ++padding; + } + + /* Print on 2nd pass if necessary */ + if ((output_enable) && (padding)) + printf(" Image padded by %d bytes\n", padding); + +/* + * Now tell the user what happened. + */ + if (output_enable) { + compression = (float)(ccount - ocount) / ((float)ccount) * 100; + fprintf(stderr, "...Compression Statistics:\n"); + fprintf(stderr, "\tinput char count = %d,", ccount); + fprintf(stderr, "output char count = %d,\n", ocount); + fprintf(stderr, "\tCompression = %2.2f%%\n", compression); + fprintf(stderr, "\trepeating records = %d,", rrecords); + fprintf(stderr, "non-repeating records = %d\n", nrecords); + fprintf(stderr, "\trepeated strings less than minimum (%d) = %d\n\n", + MINREPEAT, toosmall); + } + /* + * Return the total bytes written to the caller. + */ + return ocount; + } + + +/* + * Control output of characters and compute + * checksum and size. + */ +static void output_c(int c, FILE* f) +{ + ocount++; + if (output_enable) + fputc(c,f); + else + COMPUTE_CHECKSUM(c, head.romh.V0.checksum) +} diff --git a/util/makerom/makerom.c b/util/makerom/makerom.c new file mode 100644 index 0000000000..e29faafce3 --- /dev/null +++ b/util/makerom/makerom.c @@ -0,0 +1,675 @@ +/***************************************************************************** + +Copyright © 1994, Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, provided +that the copyright notice and this permission notice appear in all copies +of software and supporting documentation, and that the name of Digital not +be used in advertising or publicity pertaining to distribution of the software +without specific, written prior permission. Digital grants this permission +provided that you prominently mark, as not part of the original, any +modifications made to this software or documentation. + +Digital Equipment Corporation disclaims all warranties and/or guarantees +with regard to this software, including all implied warranties of fitness for +a particular purpose and merchantability, and makes no representations +regarding the use of, or the results of the use of, the software and +documentation in terms of correctness, accuracy, reliability, currentness or +otherwise; and you rely on the software, documentation and results solely at +your own risk. + +******************************************************************************/ +/* +** +** FACILITY: +** +** EBxx Software Tools - makerom +** +** FUNCTIONAL DESCRIPTION: +** +** Makerom makes roms. It takes a series of input files +** adds headers to them and outputs them either compressed +** or uncompressed (the default). This module contains the +** command parsing code. +** +** CALLING ENVIRONMENT: +** +** user mode +** +** AUTHOR: David A Rusling +** +** CREATION-DATE: 04-Feb-1994 +** +** MODIFIED BY: +** +*/ +#ifndef lint +static char *RCSid = + "$Id$"; +#endif + +/* + * $Log$ + * Revision 1.1 2001/03/22 21:26:32 rminnich + * testing I HATE CVS + * + * Revision 1.1 2000/03/21 03:56:31 stepan + * Check in current version which is a nearly a 2.2-16 + * + * Revision 1.18 1995/02/27 15:34:24 fdh + * Modified to not use 64 bit ints for portability. + * + * Revision 1.17 1995/02/25 05:14:40 fdh + * Clean up handling of options with 64bit quantities. + * Updated usage(). + * + * Revision 1.16 1995/02/16 20:45:46 fdh + * Inform user when image is padded. + * + * Revision 1.15 1995/02/10 15:44:47 fdh + * Modified image size to reflect the size after any necessary + * padding is added to align to a 32 bit boundary. + * + * Revision 1.14 1995/02/10 02:10:40 fdh + * Modified to use the COMPUTE_CHECKSUM Macro. + * + * Revision 1.13 1995/02/09 23:38:40 fdh + * Corrected char sign extension problem when computing + * checksums. + * Print out standard header summary. + * + * Revision 1.12 1995/02/08 01:23:15 fdh + * Pad to longword align the ROM image. + * ROTATE_RIGHT macro was moved to romhead.h. + * + * Revision 1.11 1995/02/07 23:16:06 fdh + * Modified the -x and -f options to work with 32 bit OS's. + * + * Revision 1.10 1995/02/07 04:51:37 fdh + * Modified to work with a change to fwid_match_i(). + * + * Revision 1.9 1995/02/07 01:00:22 fdh + * Corrected header size computation. + * Corrected comments. + * + * Revision 1.8 1995/02/06 02:42:36 fdh + * Moved some code to library file routines + * fwid_match(), fwid_match_i(), and fwid_dump(). + * + * Revision 1.7 1995/02/05 02:01:10 fdh + * Modified to accept the latest romheader definition. + * + * Revision 1.6 1995/02/02 20:19:28 fdh + * Modified to use ROM header version 1. + * Computes header and image checksums. + * Added -s -x and -f switches to specify user + * optional revision data in the header. + * Added -i switch used to specify the firmware + * ID type as either a registered string, registered + * number, or unregistered number. + * + * Revision 1.5 1995/01/23 21:23:46 fdh + * Modified to use common include file "romhead.h" + * + * Revision 1.4 1994/07/01 14:23:56 rusling + * Fixed up NT warnings. + * + * Revision 1.3 1994/03/03 16:26:09 rusling + * Fixed help text. + * + * Revision 1.6 1994/02/04 11:51:35 rusling + * Ported to Alpha WNT. + * + * Revision 1.5 1994/02/04 11:39:03 rusling + * Oops. + * + * Revision 1.3 1994/02/04 10:17:47 rusling + * Added RCS bits to the file. + * + */ + +#include +#include +#include +#include +#include "c_32_64.h" +#include "romhead.h" + +/* + * Macros + */ +#define TRUE 1 +#define FALSE 0 +#define BLOCK_SIZE 1000 + + +#define _SEEN(o) seen[o-'a'] +#define _OPTION(o) (_SEEN(o) == TRUE) + +romheader_t head; + +typedef struct fileinfo { + struct fileinfo *next; /* next file in the list */ + char *file; + struct { + ui low; + ui high; + } load; /* load point for this file */ + int32 compress; /* Should we compress this file? */ + int32 size; /* size of the file */ + int32 padding; /* padding required to longword align at the end of the file */ + int32 outputfile; /* is this an output file? */ + fw_id_t *fwid_ptr; /* Points to a predefined table */ + int fwid_alt; /* Used when user specified */ + union int_char { + char ch[8]; + struct { + ui low; + ui high; + } data; + } fwid_optional; +} fileinfo_t; +fileinfo_t *files = NULL; +fileinfo_t *last = NULL; +int32 fcount = 0; + + +int output_enable = 0; +/* + * Global data (all names preceded by 'rhdr_g'. + */ +#define SEEN_SIZE 100 +char seen[SEEN_SIZE]; /* upper and lower case */ + +/* + * Forward routine descriptions. + */ +fileinfo_t *allocate_fileinfo(); +int main(int argc, char **argv); +void process_file(fileinfo_t *ifile, FILE *out); +void usage(); +void read_file(char *filename); +void write_file(char *filename); +int32 fsize(FILE *file); +/* + * External routines. + */ +extern int compress(FILE *in, FILE *out); + +fileinfo_t *allocate_fileinfo() +{ + fileinfo_t *file; + + file = (fileinfo_t *) malloc(sizeof(fileinfo_t)); + if (file == NULL) { + fprintf(stderr, "ERROR: failed to allocate memory\n"); + exit(0); + } else { + file->load.high = 0; + file->load.low = 0; + file->size = 0; + file->compress = 0; /* no compression */ + file->file = NULL; + file->outputfile = FALSE; + } + fcount++; +/* + * return the address of the fileinfo structure to the + * caller. + */ + return file; +} + +int main(int argc, char **argv) +{ + char *arg, option; + int i; + fileinfo_t *now, *output; + FILE *out; + + for (i = 0; i < SEEN_SIZE; i++) + seen[i] = FALSE; +/* + * Allocate at least one file description block. + */ + now = last = files = allocate_fileinfo(); + now->fwid_ptr = NULL; + + if (argc < 2) { + usage(); + exit(1); + } +/* + * Parse arguments, but we are only interested in flags. + * Skip argv[0]. + */ + for (i = 1; i < argc; i++) { + arg = argv[i]; + if (*arg == '-') { + +/* + * This is a -xyz style options list. Work out the options specified. + */ + arg++; /* skip the '-' */ + while (option = *arg++) { /* until we reach the '0' string + * terminator */ + switch (option) { + case 'h': + case 'H': + usage(); + exit(1); + case 'v': /* verbose */ + case 'V': + _SEEN(tolower(option)) = TRUE; + break; + case 'C': + case 'c': +/* + * The -C,-c option means "compress the image". The compression algorithm + * is a simple removal of repeating bytes. The decompression algorithm is + * implemented in the SROM code itself. + */ + _SEEN(tolower(option)) = TRUE; + now->compress = TRUE; + break; + case 'O': + case 'o': +/* + * This file is marked as an output file. + */ + if (_SEEN(tolower(option))) { + fprintf(stderr, + "ERROR: two output file names given\n"); + exit(0); + } else { + _SEEN(tolower(option)) = TRUE; + now->outputfile = TRUE; + } + case 'L': + case 'l': +/* + * This is a special one, the -l option is followed (immediately) + * by the address where the file should be loaded into memory. + */ + _SEEN(tolower(option)) = TRUE; + { + int i, j; + char strbuf[16+1]; + + sscanf(arg, "%16s", strbuf); + i = strlen(strbuf); + + j = ((i-8)>0)?(i-8):0; + now->load.low = strtoul(&strbuf[j], NULL, 16); + strbuf[j] = '\0'; + now->load.high = strtoul(strbuf, NULL, 16); + } + arg = arg + strlen(arg); + break; + + case 'I': + case 'i': +/* + * This is a special one, the -i option is followed (immediately) + * by a firmware type identifier. + */ + _SEEN(tolower(option)) = TRUE; + + if ((now->fwid_ptr = fwid_match(arg)) == NULL) { + now->fwid_alt = atoi(arg); + now->fwid_ptr = fwid_match_i(now->fwid_alt); + } + + arg = arg + strlen(arg); + break; + + case 'X': + case 'x': +/* + * This is a special one, the -x option is followed (immediately) + * by a Hex value, truncated to 8 digits. + */ + _SEEN(tolower(option)) = TRUE; + { + int i, j; + char strbuf[16+1]; + + sscanf(arg, "%16s", strbuf); + i = strlen(strbuf); + + j = ((i-8)>0)?(i-8):0; + now->fwid_optional.data.low = strtoul(&strbuf[j], NULL, 16); + strbuf[j] = '\0'; + now->fwid_optional.data.high = strtoul(strbuf, NULL, 16); + } + arg = arg + strlen(arg); + break; + + case 'S': + case 's': +/* + * This is a special one, the -s option is followed (immediately) + * by a 8 character string. + */ + _SEEN(tolower(option)) = TRUE; + strncpy(now->fwid_optional.ch, arg, 8); + arg = arg + strlen(arg); + break; + + case 'F': + case 'f': +/* + * This is a special one, the -f option is followed (immediately) + * by a filename from which the first 8 bytes will be read and + * placed into the optional firmware ID field of the ROM header. + */ + _SEEN(tolower(option)) = TRUE; + { + FILE *inf; + int i, j; + int ch; + int quote; + char strbuf[16+1]; + + inf = fopen(arg, "rb"); + if (inf == NULL) { + fprintf(stderr, "ERROR: failed to open input file %s\n", + arg); + exit(0); + } + if (fscanf(inf, "%16s", strbuf) && isxdigit(strbuf[0])) { + i = strlen(strbuf); + + j = ((i-8)>0)?(i-8):0; + now->fwid_optional.data.low = strtoul(&strbuf[j], NULL, 16); + strbuf[j] = '\0'; + now->fwid_optional.data.high = strtoul(strbuf, NULL, 16); + } + else { + rewind(inf); + /* Ignore leading white space */ + while((ch = getc(inf)) != EOF) { + if (isspace(ch)) continue; + break; + } + + quote = FALSE; + j=0; + /* Open quote if necessary */ + /* Otherwise store the character. */ + if (ch == '"') quote = TRUE; + else + now->fwid_optional.ch[j++] = ch; + + /* Now store up to 7 more characters */ + while((ch = getc(inf)) != EOF) { + now->fwid_optional.ch[j++] = ch; + if (j > 8) break; + if (quote && (ch == '"')) break; + } + + /* Pad zero to 8 chacters if necessary */ + for (j; j<8; ++j) + now->fwid_optional.ch[j] = '\0'; + } + fclose(inf); + } + arg = arg + strlen(arg); + break; + +/* + * And now print usage and exit if we see an unrecognized switch. + */ + default: + usage(); + exit(0); + break; + } + } + } else { + fileinfo_t *new; + /* + * For each new filename supplied, create another file description + * block and put it into the file list. The last file is the output + * file. + */ + + now->file = arg; + new = allocate_fileinfo(); + new->next = NULL; + now->next = new; + last = now; + now = new; + now->fwid_ptr = NULL; + } + } +/* + * As a result of the algorithm that I've used for parsing the + * filenames and arguments into file information blocks. "last" + * points at an entry that has a pointer to an invalid (empty) + * fileinfo block. Decrement the file count also. + */ + + last->next = NULL; + fcount--; +/* + * If the world wants to know, then tell it. + */ + if _OPTION('v') { + fprintf(stderr, "makerom [V2.0]\n"); + } +/* + * Check that at least two files have been specified. + */ + if (fcount < 2) { + fprintf(stderr, "ERROR: insufficient filenames supplied\n"); + exit(0); + } + +/* + * find the output file and open it. + */ + output = files; + while (output->next != NULL) { + if (output->outputfile) + break; + output = output->next; + } + + if (!(output->outputfile)) { + fprintf(stderr, "ERROR: no output file specified\n"); + exit(0); + } + out = fopen(output->file, "wb"); + if (out == NULL) { + fprintf(stderr, "ERROR: failed to open output file %s\n", + output->file); + exit(0); + } +/* + * Now, for every file, open it, add a header and output the result + * to the output file. + */ + if _OPTION('v') + fprintf(stderr, "...Output file is %s\n\n", last->file); + now = files; + while (now->next != NULL) { + if (!(now->outputfile)) + process_file(now, out); + now = now->next; + } + /* + * close the output file and return. + */ + fclose(out); + return 0; +} /* end of main() */ + +void process_file(fileinfo_t *ifile, FILE *out) +{ + FILE *in; + char *ptr; + int32 i; + int c; +/* + * Open the input file. + * Get its size. + * Output its header. + * Output the input file's contents. + */ + + if _OPTION('v') + fprintf(stderr, "...processing input file %s\n", ifile->file); + + in = fopen(ifile->file, "rb"); + if (in == NULL) { + fprintf(stderr, "ERROR: failed to open input file %s\n", + ifile->file); + exit(0); + } + + /* Load file to get it's size */ + ifile->size = fsize(in); + +/* + * Start to build the header. + */ + head.romh.V0.signature = ROM_H_SIGNATURE; /* pattern for data path */ + head.romh.V0.csignature = (ui) ~ROM_H_SIGNATURE; /* comp pattern for data path */ + head.romh.V0.decomp = ifile->compress; /* decompression algorithm */ + head.romh.V0.hsize = /* header size */ + (ui) (((unsigned long) &head.romh.hchecksum + - (unsigned long) &head) + sizeof(head.romh.hchecksum)); + + head.romh.V0.destination.high = ifile->load.high; + head.romh.V0.destination.low = ifile->load.low; + + head.romh.V1.hversion = (char) ROM_H_REVISION; + head.romh.V0.checksum = 0; /* Initialize ROM image checksum */ + head.romh.hchecksum = 0; /* Initialize header checksum */ + head.romh.V1.rimage_size = 0; /* Initialize ROM image size */ + + /* Set FW ID optional field */ + head.romh.V1.fwoptid.id_S.high = ifile->fwid_optional.data.high; + head.romh.V1.fwoptid.id_S.low = ifile->fwid_optional.data.low; + + head.romh.V1.fw_id = + (char) ((ifile->fwid_ptr != NULL) ? ifile->fwid_ptr->firmware_id : ifile->fwid_alt); + + /* + * Make a pass on the input file to compute the ROM image checksum. + */ + output_enable = FALSE; /* <-FALSE, Compute checksum only */ + if (ifile->compress) { /* Do we compress this file? */ + head.romh.V1.rimage_size = compress(in, out); + head.romh.V0.size = ifile->size; /* Uncompressed size */ + } + else { + for (i = 0; i < ifile->size; ++i) { + if ((c = getc(in)) == EOF) + abort(); + COMPUTE_CHECKSUM(c,head.romh.V0.checksum); + ++head.romh.V1.rimage_size; /* Write out the ROM image size */ + } + ifile->padding = 0; + while(((ifile->size+ifile->padding)%4) != 0) { + ++ifile->padding; + COMPUTE_CHECKSUM('\0',head.romh.V0.checksum); + ++head.romh.V1.rimage_size; /* Write out the ROM image size */ + } + + if (ifile->padding) + printf(" Image padded by %d bytes\n", ifile->padding); + + head.romh.V0.size = head.romh.V1.rimage_size; /* Same size, No compression */ + } + + rewind(in); /* Back to the start of the input file. */ + +/* + * Compute the header checksum. + */ + head.romh.hchecksum = compute_romh_chksum(&head); + +/* + * Now write out the header. + */ + ptr = (char *) &head; + for (i = 0; i < (int) head.romh.V0.hsize; i++) + fputc(*ptr++, out); + +/* + * print out header summary. + */ + if _OPTION('v') dumpHeader(&head); + +/* + * Second pass. The checksums have been computed and the header + * has already been written out so produce the output file this time. + */ + output_enable = TRUE; /* <-TRUE, Output file this time */ + if (ifile->compress) /* Do we compress this file? */ + compress(in, out); + else { +/* + * Now read in the input file again and output it. + */ + for (i = 0; i < ifile->size; ++i) { + if ((c = getc(in)) == EOF) + abort(); + fputc(c, out); + } + /* Pad to longword align the end of the file */ + for (i=0; ipadding; ++i) + fputc('\0', out); + } + +/* + * Finally, close the input file. + */ + fclose(in); +} +void usage() +{ + printf("\nmakerom [options] []...-o \n\n"); + printf("Builds a rom image by adding headers to the input files.\n"); + printf("The input files and headers and concatenated and written\n"); + printf("to the output file. Optionally, those input files may also be\n"); + printf("compressed\n\n"); + printf("Where each input file is preceded by options:\n"); + printf("\t-l,L
= load address in memory of the image\n"); + printf("\t-c,C = compress this file (the SROM code decompresses\n"); + printf("\t\tthe image). The default is no compression\n"); + printf("\t-x,X = Sets optional firmware ID field.\n"); + printf("\t-s,S<8 char string> = Sets optional firmware ID field.\n"); + printf("\t-f,F = Sets optional firmware ID field.\n"); + printf("\t\tWhere the file contains either a hex value or\n"); + printf("\t\ta \"quoted\" ASCII string.\n\n"); + printf("\t-i,I = Firmware ID string or number.\n"); + printf("\t\tThe following pre-defined values can also be used...\n"); + + fwid_dump("\t\t "); + + printf("\nOptional flags are:\n"); + printf("\t-v,V = verbose mode\n"); + printf("\t-h,H = print this help text\n"); + printf("\nExample:\n"); + printf("\tmakerom -v -l200000 eb66_rom.img -o eb66_rom.rom\n"); + +} + + +int32 fsize(FILE *fp) +{ + int c; + int32 size = 0; + + fseek(fp, 0, 0); + while ((c = getc(fp)) != EOF) + size++; + fseek(fp, 0, 0); + return size; +}