diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c
index 4838a4e976..d1a65655d3 100644
--- a/src/lib/fallback_boot.c
+++ b/src/lib/fallback_boot.c
@@ -15,6 +15,7 @@ void boot_successful(void)
 	outb(index, RTC_PORT(0));
 
 	byte = inb(RTC_PORT(1));
+	byte &= 0xfe;
 	byte |= (byte & 2) >> 1;
 	outb(byte, RTC_PORT(1));
 }
diff --git a/src/lib/serial_subr.c b/src/lib/serial_subr.c
index 131a0e893d..2de21b3cab 100644
--- a/src/lib/serial_subr.c
+++ b/src/lib/serial_subr.c
@@ -4,6 +4,8 @@ static char rcsid[] = "$Id$";
 
 #include <arch/io.h>
 #include <serial_subr.h>
+#include <printk.h>
+#include <pc80/mc146818rtc.h>
 
 /* Base Address */
 #ifndef TTYS0_BASE
@@ -155,7 +157,14 @@ inline void uart_init(unsigned base_port, unsigned divisor)
 
 void ttys0_init(void)
 {
-	uart_init(TTYS0_BASE, TTYS0_DIV);
+	static unsigned char div[8]={1,2,3,6,12,24,48,96};
+	int b_index=0;
+	unsigned int divisor=TTYS0_DIV;
+
+	if(get_option(&b_index,"baud_rate")==0) {
+		divisor=div[b_index];
+	}
+	uart_init(TTYS0_BASE, divisor);
 }
 
 void ttys0_tx_byte(unsigned char data) 
diff --git a/src/lib/subr.c b/src/lib/subr.c
index 837d7f6aa0..d38d75a53b 100644
--- a/src/lib/subr.c
+++ b/src/lib/subr.c
@@ -14,6 +14,7 @@ static char rcsid[] = "$Id$";
 #include <pci.h>
 #include <subr.h>
 #include <string.h>
+#include <pc80/mc146818rtc.h>
 
 #ifdef SERIAL_CONSOLE
 #include <serial_subr.h>
@@ -29,6 +30,8 @@ static char rcsid[] = "$Id$";
 // initialize the display
 void displayinit(void)
 {
+	get_option(&console_loglevel, "debug_level");
+
 #ifdef VIDEO_CONSOLE
 	video_init();
 #endif
diff --git a/src/northbridge/intel/82860/rdram_setup.c b/src/northbridge/intel/82860/rdram_setup.c
index a9a1fc9086..1275901315 100644
--- a/src/northbridge/intel/82860/rdram_setup.c
+++ b/src/northbridge/intel/82860/rdram_setup.c
@@ -15,6 +15,7 @@
 #include <superio/generic.h>
 #include <superio/w83627hf.h>
 #include <northbridge/intel/82860/rdram.h>
+#include <pc80/mc146818rtc.h>
 
 #define LPC_BUS 0
 #define LPC_DEVFN ((0x1f << 3) + 0)
@@ -605,7 +606,7 @@ void mch_init(void)
 	/* Memory Controller Hub Configuration */
 	/* 1 System Bus Stop Grant,300 or 400Mhz, Non-ECC, MDA Not Present, Apic Enabled */
 	pcibios_read_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_MCHCFG, &word); 
-	word &= ~((7 << 13) | (1 << 9) | (3 << 7) | (1 << 5) | (1 << 1));
+	word &= ~((7 << 13) | (1 << 11) | (1 << 9) | (3 << 7) | (1 << 5) | (1 << 1));
  	if(((spd_mhz_max[0]==400)&&(spd_mhz_max[1]==400)) ||
 	   ((spd_mhz_max[0]==400)&&(spd_mhz_max[1]==0)))
 		word |= (1 << 11);  /* Sets ram bus speed at 400 mhz, else 300 mhz */
@@ -773,6 +774,7 @@ static void ram_zap(unsigned long start, unsigned long stop)
 void init_memory(void)
 {
 	int i,j;
+	int ecc=1;
 	int rdram_devices=0;
 	u32 ricm;
 	u16 word;
@@ -849,9 +851,12 @@ void init_memory(void)
 		MCH_RICM, ricm);
 	
 	/* Memory Controller Hub Configuration Enable ECC */
-	pcibios_read_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_MCHCFG, &word); 
-	word |= (1 << 8);
-	pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_MCHCFG, word); 
+	get_option(&ecc,"ECC_memory");
+	if((ecc)&&(spd_data_width[0]==18)) {  /* ECC is enables, so turn it on */
+		pcibios_read_config_word(I860_MCH_BUS,I860_MCH_DEVFN,MCH_MCHCFG, &word);
+		word |= (1 << 8);
+		pcibios_write_config_word(I860_MCH_BUS,I860_MCH_DEVFN,MCH_MCHCFG,word);
+	}
 
 	/* Set write combine for the memory max of 2 gig */
 	printk_debug("set_var_mtrr\n");
diff --git a/src/pc80/mc146818rtc.c b/src/pc80/mc146818rtc.c
index 1bb253c428..f559ea89a0 100644
--- a/src/pc80/mc146818rtc.c
+++ b/src/pc80/mc146818rtc.c
@@ -173,7 +173,7 @@ void rtc_init(int invalid)
 	      length = number of bits to include in the value
 	      ret = a character pointer to where the value is to be returned
 	output the value placed in ret
-	      returns 1 = successful, 0 = an error occurred
+	      returns 0 = successful, -1 = an error occurred
 */
 static int get_cmos_value(unsigned long bit, unsigned long length, void *vret)
 {
diff --git a/src/pc80/serial.inc b/src/pc80/serial.inc
index 777c13cd44..94ce874871 100644
--- a/src/pc80/serial.inc
+++ b/src/pc80/serial.inc
@@ -1,3 +1,6 @@
+#include <part/fallback_boot.h>
+
+
 /* Base Address */
 #ifndef TTYS0_BASE
 #define TTYS0_BASE	0x3f8
@@ -41,6 +44,16 @@
 #define TTYS0_MSR (TTYS0_BASE+0x06)
 #define TTYS0_SCR (TTYS0_BASE+0x07)
 
+#if USE_OPTION_TABLE == 1
+.section ".rom.data"
+	.type	 div,@object
+	.size	 div,8
+div:
+.byte 1,2,3,5,12,24,48,96
+
+.previous
+#endif
+
 	jmp	serial0
 
 	/* uses:	ax, dx */
@@ -63,13 +76,28 @@ serial0:
 	out	%al, %dx
 
 	/* set Baud Rate Divisor to 1 ==> 115200 Buad */
+#if USE_OPTION_TABLE == 1
+	movb	$RTC_BOOT_BYTE, %al
+	outb	%al, $0x70
+	xorl	%edx,%edx
+	inb	$0x71, %al
+	sarb	$2,%al
+	andb	$7,%al
+	movb	%al,%dl
+	movb	div(%edx),%al
+	mov	$TTYS0_DLL, %dx
+	out	%al, %dx
+	mov	$TTYS0_DLM, %dx
+	xorb	%al,%al
+	out	%al, %dx
+#else
 	mov	$TTYS0_DLL, %dx
 	mov	$TTYS0_DIV_LO, %al
 	out	%al, %dx
 	mov	$TTYS0_DLM, %dx
 	mov	$TTYS0_DIV_HI, %al
 	out	%al, %dx
-
+#endif
 	/* Disable DLAB */
 	mov	$TTYS0_LCR, %dx
 	mov	$(TTYS0_LCS & 0x7f), %al
diff --git a/src/southbridge/intel/82801/cmos_failover.inc b/src/southbridge/intel/82801/cmos_failover.inc
index 453dd880f2..48691cdb20 100644
--- a/src/southbridge/intel/82801/cmos_failover.inc
+++ b/src/southbridge/intel/82801/cmos_failover.inc
@@ -64,7 +64,8 @@ __failover_boot:
 __rtc_failed:
 	movb	$RTC_BOOT_BYTE, %al
 	outb	%al, $0x70
-	xorb	%al, %al
+	inb	$0x71, %al
+	andb	$0xfc, %al
 	outb	%al, $0x71
 	jmp	__rtc_ok