UPSTREAM: AMD/spi: Do not reset fifo after skipping the sent bytes

After we skip the bytes we send, the fifo pointer is at
right position. Reseting the fifo will change it to a
wrong place.

Please view the flashrom code, which tells the same thing.
https://code.coreboot.org/p/flashrom/source/tree/HEAD/trunk/sb600spi.c#L257

Change-Id: I31d487ce32c0d7ca3dead36d2b14611e73b1ad60
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/14955
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/348213
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/southbridge/amd/agesa/hudson/spi.c

@@ -143,7 +143,6 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
 		cmd = spi_read(SPI_REG_FIFO);
 	}
 
-	reset_internal_fifo_pointer();
 	for (count = 0; count < bytesin; count++, din++) {
 		*(uint8_t *)din = spi_read(SPI_REG_FIFO);
 	}