From f9f81e483941c7b5741430e306a122a5644e3630 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 18 Feb 2026 20:39:35 +0100
Subject: [PATCH] mb/lenovo/x220: Replace CFR enums with booleans

Commit f530d37da736 ("mb/lenovo/x220: Add PCIe ports in CFR") introduced
several enum options for "Enabled"/"Disabled" settings. These work like
bool options, except that they add extra bloat to the resulting CFR data
structures.

Replace the enum options with bool options. Also rename the macro as it
no longer generates an enum option. While we're at it, properly format
"Wi-Fi" and drop a blank line at the start of a file.

Also, since checkpatch complains about the macro including a trailing
semicolon, drop it from the macro definition and add it at the end of
every use of the macro.

Change-Id: I7889e22d12e01171ed77ae98d29bbd067e45d82b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91340
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/mainboard/lenovo/x220/cfr.c     |  9 ++++-----
 src/southbridge/intel/bd82x6x/cfr.h | 18 +++++++-----------
 2 files changed, 11 insertions(+), 16 deletions(-)

diff --git a/src/mainboard/lenovo/x220/cfr.c b/src/mainboard/lenovo/x220/cfr.c
index 2ebfd32d77..e37464a07a 100644
--- a/src/mainboard/lenovo/x220/cfr.c
+++ b/src/mainboard/lenovo/x220/cfr.c
@@ -1,4 +1,3 @@
-
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
@@ -8,12 +7,12 @@
 #include <northbridge/intel/sandybridge/cfr.h>
 #include <southbridge/intel/bd82x6x/cfr.h>
 
-GEN_RP_ENUM(1, "Wifi")
+DEFINE_RP_ENABLE_OPTION(1, "Wi-Fi");
 #if CONFIG(BOARD_LENOVO_X220)
-GEN_RP_ENUM(3, "ExpressCard")
+DEFINE_RP_ENABLE_OPTION(3, "ExpressCard");
 #endif
-GEN_RP_ENUM(4, "SD Card Reader")
-GEN_RP_ENUM(6, "xHCI")
+DEFINE_RP_ENABLE_OPTION(4, "SD Card Reader");
+DEFINE_RP_ENABLE_OPTION(6, "xHCI");
 
 static struct sm_obj_form pcie = {
 	.ui_name = "PCH PCIe",
diff --git a/src/southbridge/intel/bd82x6x/cfr.h b/src/southbridge/intel/bd82x6x/cfr.h
index d70650463a..064636d6b5 100644
--- a/src/southbridge/intel/bd82x6x/cfr.h
+++ b/src/southbridge/intel/bd82x6x/cfr.h
@@ -11,17 +11,13 @@
 #include <southbridge/intel/common/pmutil.h>
 #include "me.h"
 
-#define GEN_RP_ENUM(x, y)					\
-static const struct sm_object pcie_rp##x = SM_DECLARE_ENUM({	\
-	.opt_name	= "pch_pcie_enable_rp"#x,		\
-	.ui_name	= y,					\
-	.ui_helptext	= "Enable or disable "#y,		\
-	.default_value	= 1,					\
-	.values		= (const struct sm_enum_value[]) {	\
-		{ "Disabled",	0	},			\
-		{ "Enabled",	1	},			\
-		SM_ENUM_VALUE_END	},			\
-});
+#define DEFINE_RP_ENABLE_OPTION(_rp, _name)			\
+static const struct sm_object pcie_rp##_rp = SM_DECLARE_BOOL({	\
+	.opt_name	= "pch_pcie_enable_rp"#_rp,		\
+	.ui_name	= _name,				\
+	.ui_helptext	= "Enable or disable "#_name,		\
+	.default_value	= true,					\
+})
 
 /* Power state after power loss */
 static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({