From f9dc2a8d8016fa7db974fb6cb01c3275e26832af Mon Sep 17 00:00:00 2001
From: David Hendricks <dhendrix@chromium.org>
Date: Thu, 17 Oct 2013 19:09:31 -0700
Subject: [PATCH] tegra124: add a #define for DMA alignment size

BUG=none
BRANCH=none
TEST=used in SPI driver

Change-Id: I2b348660f38fb181c5a4dcf23091c9740af8b042
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173638
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: David James <davidjames@chromium.org>
---
 src/soc/nvidia/tegra124/dma.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/nvidia/tegra124/dma.h b/src/soc/nvidia/tegra124/dma.h
index bfbf7b867d..d7e9090c0f 100644
--- a/src/soc/nvidia/tegra124/dma.h
+++ b/src/soc/nvidia/tegra124/dma.h
@@ -22,6 +22,12 @@
 #include <inttypes.h>
 #include <soc/addressmap.h>
 
+/*
+ * The DMA engine operates on 4 bytes at a time, so make sure any data
+ * passed via DMA is aligned to avoid underrun/overrun.
+ */
+#define TEGRA_DMA_ALIGN_BYTES	4
+
 struct apb_dma_channel_regs {
 	u32 csr;		/* 0x00 */
 	u32 sta;		/* 0x04 */