From f9d6fd4e0f0b7c5cd352adaa55887043b5c86a3b Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 12 Dec 2024 10:45:44 +0100 Subject: [PATCH] soc/intel/xeon_sp: Enable IDT_IN_EVERY_STAGE Make use of exception handling in every stage. Additionally this enables breakpoints in all stages, making NULL dereferences and stack overflows easier to detect. TEST: Stack canary exceptions are seen in romstage on ibm/sbp1. Change-Id: I8a9f12b9ae041ce47c14f2ef7f09b029d408260e Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/85569 Reviewed-by: Shuo Liu Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index e1a4ac54c9..f61de56105 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -46,6 +46,7 @@ config XEON_SP_COMMON_BASE select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select IDT_IN_EVERY_STAGE if XEON_SP_COMMON_BASE