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UPSTREAM: nb/intel/x4x/raminit: Initialise async variable

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It could end up not initialized which causes it not to build with
clang.

BUG=none
BRANCH=none
TEST=none

Change-Id: I295a03b36c881c157fd8ae00cace1686d67089ee
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 37689fae38
Original-Change-Id: I3be9477d836123aaa87c9bebb41c1ec34689a771
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19736
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/514191
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Arthur Heymans 2017-05-17 14:07:10 +02:00 • committed by chrome-bot
commit f9c53acfeb
1 changed files with 1 additions and 1 deletions
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2
src/northbridge/intel/x4x/raminit_ddr2.c
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@ -714,7 +714,7 @@ static void timings_ddr2(struct sysinfo *s)
static void dll_ddr2(struct sysinfo *s)
{
u8 i, j, r, reg8, clk, async;
u8 i, j, r, reg8, clk, async = 0;
u16 reg16 = 0;
u32 reg32 = 0;
u8 lane;