From f789899dac82dc13a50504f71efd1790b63baf8d Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sat, 26 Jul 2025 09:35:08 +0200 Subject: [PATCH] sb/intel/common/gpio: Move register defines Move ICH7 GPIO register defines into private scope. This enforces the use of GPIO common code and mainboard can no longer directly access GPIO I/O registers. Change-Id: Iedf3e55f8aecf7b1ac6f47b29d9f88d58d1b6867 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/88568 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/common/gpio.c | 22 ++++++++++++++++++++++ src/southbridge/intel/common/gpio.h | 16 ---------------- 2 files changed, 22 insertions(+), 16 deletions(-) diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 681457d51c..ae13cb95bf 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -12,9 +12,31 @@ #define MAX_GPIO_NUMBER 75 /* zero based */ +/* + * If you want to use these macros outside this file, consider making + * more helper functions to expose the functionality you want instead. + */ + /* LPC GPIO Base Address Register */ #define GPIO_BASE 0x48 +/* ICH7 GPIOBASE */ +#define GPIO_USE_SEL 0x00 +#define GP_IO_SEL 0x04 +#define GP_LVL 0x0c +#define GPO_BLINK 0x18 +#define GPI_INV 0x2c +#define GPIO_USE_SEL2 0x30 +#define GP_IO_SEL2 0x34 +#define GP_LVL2 0x38 +#define GPIO_USE_SEL3 0x40 +#define GP_IO_SEL3 0x44 +#define GP_LVL3 0x48 +#define GP_RST_SEL1 0x60 +#define GP_RST_SEL2 0x64 +#define GP_RST_SEL3 0x68 + + static u16 get_gpio_base(void) { #ifdef __SIMPLE_DEVICE__ diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h index 4502d8f157..3d7bebf3c1 100644 --- a/src/southbridge/intel/common/gpio.h +++ b/src/southbridge/intel/common/gpio.h @@ -7,22 +7,6 @@ #include #include -/* ICH7 GPIOBASE */ -#define GPIO_USE_SEL 0x00 -#define GP_IO_SEL 0x04 -#define GP_LVL 0x0c -#define GPO_BLINK 0x18 -#define GPI_INV 0x2c -#define GPIO_USE_SEL2 0x30 -#define GP_IO_SEL2 0x34 -#define GP_LVL2 0x38 -#define GPIO_USE_SEL3 0x40 -#define GP_IO_SEL3 0x44 -#define GP_LVL3 0x48 -#define GP_RST_SEL1 0x60 -#define GP_RST_SEL2 0x64 -#define GP_RST_SEL3 0x68 - #define GPIO_MODE_NATIVE 0 #define GPIO_MODE_GPIO 1 #define GPIO_MODE_NONE 1