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soc/amd/cezanne,soc/intel/common: rework CPPC table generation

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Make use of the newly introduced ACPI macros for CPPC table generation
that currently exists of a bunch of confusing assignments of structs
that only get partially filled.

Test: dumped SSDT before and after do not differ.

Change-Id: I844d191b1134b98e409240ede71e2751e51e2159
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lance Zhao
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Michael Niewöhner 2021-10-05 21:42:57 +02:00 • committed by Felix Held
commit f72c7b154d
3 changed files with 63 additions and 322 deletions
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169
src/soc/amd/cezanne/cppc.c
View file

@ -13,156 +13,37 @@
*/
void cpu_init_cppc_config(struct cppc_config *config, u32 version)
{
acpi_addr_t msr = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 8,
.bit_offset = 0,
.access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS,
.addrl = 0,
.addrh = 0,
};
static const acpi_addr_t unsupported = {
.space_id = ACPI_ADDRESS_SPACE_MEMORY,
.bit_width = 0,
.bit_offset = 0,
.access_size = ACPI_ACCESS_SIZE_UNDEFINED,
.addrl = 0,
.addrh = 0,
};
config->version = version;
/*
* Highest Performance:
*/
msr.addrl = MSR_CPPC_CAPABILITY_1;
msr.bit_offset = SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF;
config->regs[CPPC_HIGHEST_PERF] = msr;
config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
config->regs[CPPC_NOMINAL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
config->regs[CPPC_GUARANTEED_PERF] = ACPI_REG_UNSUPPORTED;
config->regs[CPPC_DESIRED_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
config->regs[CPPC_MIN_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
config->regs[CPPC_MAX_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
config->regs[CPPC_PERF_REDUCE_TOLERANCE] = ACPI_REG_UNSUPPORTED;
config->regs[CPPC_TIME_WINDOW] = ACPI_REG_UNSUPPORTED;
config->regs[CPPC_COUNTER_WRAP] = ACPI_REG_UNSUPPORTED;
config->regs[CPPC_REF_PERF_COUNTER] = ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
config->regs[CPPC_DELIVERED_PERF_COUNTER] = ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
config->regs[CPPC_PERF_LIMITED] = ACPI_REG_MSR(MSR_CPPC_STATUS, 1, 1);
config->regs[CPPC_ENABLE] = ACPI_REG_MSR(MSR_CPPC_ENABLE, 0, 1);
/*
* Lowest Nonlinear Performance -> Most Efficient Performance:
*/
msr.bit_offset = SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF;
config->regs[CPPC_LOWEST_NONL_PERF] = msr;
if (version < 2)
return;
/*
* Lowest Performance:
*/
msr.bit_offset = SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF;
config->regs[CPPC_LOWEST_PERF] = msr;
config->regs[CPPC_AUTO_SELECT] = ACPI_REG_UNSUPPORTED;
config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = ACPI_REG_UNSUPPORTED;
config->regs[CPPC_PERF_PREF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
config->regs[CPPC_REF_PERF] = ACPI_REG_UNSUPPORTED;
/*
* Guaranteed Performance Register:
*/
config->regs[CPPC_GUARANTEED_PERF] = unsupported;
if (version < 3)
return;
/*
* Nominal Performance -> Maximum Non-Turbo Ratio:
*/
msr.bit_offset = SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF;
config->regs[CPPC_NOMINAL_PERF] = msr;
/*
* Desired Performance Register:
*/
msr.addrl = MSR_CPPC_REQUEST;
msr.bit_offset = SHIFT_CPPC_REQUEST_DES_PERF;
config->regs[CPPC_DESIRED_PERF] = msr;
/*
* Minimum Performance Register:
*/
msr.bit_offset = SHIFT_CPPC_REQUEST_MIN_PERF;
config->regs[CPPC_MIN_PERF] = msr;
/*
* Maximum Performance Register:
*/
msr.bit_offset = SHIFT_CPPC_REQUEST_MAX_PERF;
config->regs[CPPC_MAX_PERF] = msr;
/*
* Performance Reduction Tolerance Register:
*/
config->regs[CPPC_PERF_REDUCE_TOLERANCE] = unsupported;
/*
* Time Window Register:
*/
config->regs[CPPC_TIME_WINDOW] = unsupported;
/*
* Counter Wraparound Time:
*/
config->regs[CPPC_COUNTER_WRAP] = unsupported;
/*
* Reference Performance Counter Register:
*/
msr.addrl = MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT;
msr.bit_width = 64;
msr.bit_offset = 0;
config->regs[CPPC_REF_PERF_COUNTER] = msr;
/*
* Delivered Performance Counter Register:
*/
msr.addrl = MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT;
config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr;
/*
* Performance Limited Register:
*/
msr.bit_width = 1;
msr.addrl = MSR_CPPC_STATUS;
msr.bit_offset = 1;
config->regs[CPPC_PERF_LIMITED] = msr;
/*
* CPPC Enable Register:
*/
msr.addrl = MSR_CPPC_ENABLE;
msr.bit_offset = 0;
config->regs[CPPC_ENABLE] = msr;
if (version >= 2) {
/* Autonomous Selection Enable is populated below */
/*
* Autonomous Activity Window Register
*/
config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = unsupported;
/*
* Autonomous Energy Performance Preference Register
*/
msr.addrl = MSR_CPPC_REQUEST;
msr.bit_width = 8;
msr.bit_offset = SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF;
config->regs[CPPC_PERF_PREF] = msr;
/* Reference Performance */
config->regs[CPPC_REF_PERF] = unsupported;
if (version >= 3) {
/* Lowest Frequency */
config->regs[CPPC_LOWEST_FREQ] = unsupported;
/* Nominal Frequency */
config->regs[CPPC_NOMINAL_FREQ] = unsupported;
}
/*
* Autonomous Selection Enable = 1
* This field is actually the first addition in version 2 but
* it's so unlike the others I'm populating it last.
*/
msr.space_id = ACPI_ADDRESS_SPACE_MEMORY;
msr.bit_width = 32;
msr.bit_offset = 0;
msr.access_size = ACPI_ACCESS_SIZE_UNDEFINED;
msr.addrl = 1;
config->regs[CPPC_AUTO_SELECT] = unsupported;
}
config->regs[CPPC_LOWEST_FREQ] = ACPI_REG_UNSUPPORTED;
config->regs[CPPC_NOMINAL_FREQ] = ACPI_REG_UNSUPPORTED;
}