From f7255d8c5543b7e98a7f83ad1ebb604a8948928b Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 30 Sep 2013 15:19:11 -0700 Subject: [PATCH] ARM: Hack out assembly barriers when on tegra124. The tegra124 AVP uses ARMv4 which doesn't support the barrier assembly instructions. Unfortunately we assume that we can (and should) use those during the bootblock and things don't build. In place of a more robust long term solution, we can just chop those out on boards with the tegra124. This is only supposed to be a short term, stop gap solution. BUG=None TEST=Built for pit, nyan. Booted into the bootblock on nyan. BRANCH=None Change-Id: Ifd0bfd3f7e30df6b5bcb1222c070922b81136b03 Signed-off-by: Gabe Black Reviewed-on: https://chromium-review.googlesource.com/171151 Reviewed-by: Julius Werner Tested-by: Gabe Black Commit-Queue: Gabe Black --- src/arch/armv7/include/arch/cache.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 1cd9958fc4..437be83063 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -32,6 +32,7 @@ #ifndef ARMV7_CACHE_H #define ARMV7_CACHE_H +#include #include #include @@ -74,19 +75,25 @@ /* data memory barrier */ static inline void dmb(void) { +#if !defined(CONFIG_SOC_NVIDIA_TEGRA124) || !defined(__BOOT_BLOCK__) asm volatile ("dmb" : : : "memory"); +#endif } /* data sync barrier */ static inline void dsb(void) { +#if !defined(CONFIG_SOC_NVIDIA_TEGRA124) || !defined(__BOOT_BLOCK__) asm volatile ("dsb" : : : "memory"); +#endif } /* instruction sync barrier */ static inline void isb(void) { +#if !defined(CONFIG_SOC_NVIDIA_TEGRA124) || !defined(__BOOT_BLOCK__) asm volatile ("isb" : : : "memory"); +#endif } /*