From f6d40a95644bdb5df8043ba94888d1c29f738731 Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Tue, 25 Feb 2025 16:56:12 +0100 Subject: [PATCH] soc/amd/picasso/chipset.cb: Enable gpp_bridge_[a/b] by default Since FSP doesn't support disabling bridges and has no UPDs for that, they must be enabled in DT to make sure they are properly initialized during PCI enumeration as expected by the payload (EDK2 for example). It might be OK to have them set to off when all devices behind the bridge are also off and FSP disables those secondary devices. In general something that cannot be hidden/shut off shouldn't be marked as such, as later stages (payload/OS) might find it active, but unconfigured. Change-Id: I4104a6af00304b0a7c50ba0e09ad19a0ed9d2733 Signed-off-by: Maximilian Brune Reviewed-on: https://review.coreboot.org/c/coreboot/+/86598 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- .../google/zork/variants/baseboard/dalboz/devicetree.cb | 1 + .../google/zork/variants/baseboard/trembyle/devicetree.cb | 1 + src/soc/amd/picasso/chipset.cb | 4 ++-- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb index e8b73ca900..4af7231eb9 100644 --- a/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb @@ -344,6 +344,7 @@ chip soc/amd/picasso device ref hda off end # HDA device ref mp2 on end # non-Sensor Fusion Hub device end + device ref internal_bridge_b off end # internal bridge to bus B device ref lpc_bridge on chip ec/google/chromeec device pnp 0c09.0 alias cros_ec on diff --git a/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb index d6f2136c81..9b5a4c05db 100644 --- a/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb @@ -370,6 +370,7 @@ chip soc/amd/picasso device ref hda off end # HDA device ref mp2 on end # non-Sensor Fusion Hub device end + device ref internal_bridge_b off end # internal bridge to bus B device ref lpc_bridge on chip ec/google/chromeec device pnp 0c09.0 alias cros_ec on diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb index c11d502f16..a254ceacb5 100644 --- a/src/soc/amd/picasso/chipset.cb +++ b/src/soc/amd/picasso/chipset.cb @@ -17,7 +17,7 @@ chip soc/amd/picasso device pci 01.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end device pci 01.7 alias gpp_bridge_6 off ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy device function, do not disable - device pci 08.1 alias internal_bridge_a off # internal bridge to bus A + device pci 08.1 alias internal_bridge_a on # internal bridge to bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # internal GPU device pci 0.1 alias gfx_hda off end # display HD Audio controller @@ -32,7 +32,7 @@ chip soc/amd/picasso device pci 0.6 alias hda off end # main HD Audio Controller device pci 0.7 alias mp2 off end # sensor fusion hub (MP2) end - device pci 08.2 alias internal_bridge_b off # internal bridge to bus B + device pci 08.2 alias internal_bridge_b on # internal bridge to bus B ops amd_internal_pcie_gpp_ops device pci 0.0 alias sata off ops amd_sata_ops end device pci 0.1 alias xgbe_0 off end