From f676cffb2d81f79d00d065f8246e86f9e2a1dbe0 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Tue, 28 Jan 2025 17:03:11 +0000 Subject: [PATCH] soc/intel/skylake: Change the maximum C state to C8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The EDS says that SkyLake "supports C0, C2, C3, C6, C8, and C10 package states". Update the highest state for non-S0ix boards accordingly. Change-Id: I9f0bf7c4d1ccc04b3ceae8b5f1d492dd6faa77e0 Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/86201 Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 3a60adad50..76940334d7 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -124,7 +124,7 @@ static int cstate_set_s0ix[] = { static int cstate_set_non_s0ix[] = { C_STATE_C1E, C_STATE_C3, - C_STATE_C7S_LONG_LAT, + C_STATE_C8 }; const acpi_cstate_t *soc_get_cstate_map(size_t *entries)