From f6286232172b4472da3249a443b2b9a7fcaa35f9 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 31 Mar 2017 13:49:31 -0700 Subject: [PATCH] UPSTREAM: soc/intel/skylake: Add tsc_freq.c to verstage This is required to provide tsc freq required by timer library. BUG=b:35583330 TEST=Verified that delay(5) in verstage adds a delay of 5 seconds. Change-Id: I0b513dabd0a3f8ff3e5a52717d70757c709e7f1e Signed-off-by: Patrick Georgi Original-Commit-Id: 3255839be15bcccde652891354e91965733f8a86 Original-Change-Id: I03edebe394522516b46125fae1a17e9a06fd5f45 Original-Signed-off-by: Furquan Shaikh Original-Reviewed-on: https://review.coreboot.org/19094 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Paul Menzel Reviewed-on: https://chromium-review.googlesource.com/471455 --- src/soc/intel/skylake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index f7b4971869..f9c267e435 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -33,6 +33,7 @@ verstage-$(CONFIG_UART_DEBUG) += uart_debug.c verstage-y += pmutil.c verstage-y += bootblock/i2c.c verstage-y += spi.c +verstage-y += tsc_freq.c romstage-y += flash_controller.c romstage-y += gpio.c