diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc
index aebaca0a0b..e54e365a4b 100644
--- a/src/mainboard/google/auron/Makefile.inc
+++ b/src/mainboard/google/auron/Makefile.inc
@@ -24,6 +24,9 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
+romstage-y += pei_data.c
+ramstage-y += pei_data.c
+
 ## DIMM SPD for on-board memory
 romstage-y += spd.c
 SPD_BIN = $(obj)/spd.bin
diff --git a/src/mainboard/google/auron/pei_data.c b/src/mainboard/google/auron/pei_data.c
new file mode 100644
index 0000000000..7277b8104c
--- /dev/null
+++ b/src/mainboard/google/auron/pei_data.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <broadwell/gpio.h>
+#include <broadwell/pei_data.h>
+#include <broadwell/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	pei_data->ec_present = 1;
+
+	/* One installed DIMM per channel -- can be changed by SPD init */
+	pei_data->dimm_channel0_disabled = 2;
+	pei_data->dimm_channel1_disabled = 2;
+
+	/* P0: LTE */
+	pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_MINI_PCIE);
+	/* P1: POrt A, CN10 */
+	pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
+			   USB_PORT_BACK_PANEL);
+	/* P2: CCD */
+	pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+	/* P3: BT */
+	pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_MINI_PCIE);
+	/* P4: Port B, CN6 */
+	pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
+			   USB_PORT_BACK_PANEL);
+	/* P5: EMPTY */
+	pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
+			   USB_PORT_SKIP);
+	/* P6: SD Card */
+	pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_FLEX);
+	/* P7: EMPTY */
+	pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
+			   USB_PORT_SKIP);
+
+	/* P1: Port A, CN6 */
+	pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+	/* P2: EMPTY */
+	pei_data_usb3_port(pei_data, 1, 0, USB_OC_PIN_SKIP, 0);
+	/* P3: EMPTY */
+	pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
+	/* P4: EMPTY */
+	pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
+}
diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c
index 7d84a1372b..b52d277265 100644
--- a/src/mainboard/google/auron/romstage.c
+++ b/src/mainboard/google/auron/romstage.c
@@ -73,59 +73,7 @@ const struct rcba_config_instruction rcba_config[] = {
 
 void mainboard_romstage_entry(unsigned long bist)
 {
-	struct pei_data pei_data = {
-		pei_version: PEI_VERSION,
-		mchbar: DEFAULT_MCHBAR,
-		dmibar: DEFAULT_DMIBAR,
-		epbar: DEFAULT_EPBAR,
-		pciexbar: DEFAULT_PCIEXBAR,
-		smbusbar: SMBUS_IO_BASE,
-		wdbbar: 0x4000000,
-		wdbsize: 0x1000,
-		hpet_address: HPET_ADDR,
-		rcba: DEFAULT_RCBA,
-		pmbase: DEFAULT_PMBASE,
-		gpiobase: DEFAULT_GPIOBASE,
-		temp_mmio_base: 0xfed08000,
-		system_type: 5, /* ULT */
-		tseg_size: CONFIG_SMM_TSEG_SIZE,
-		spd_addresses: { 0xff, 0x00, 0xff, 0x00 },
-		ec_present: 1,
-		// 0 = leave channel enabled
-		// 1 = disable dimm 0 on channel
-		// 2 = disable dimm 1 on channel
-		// 3 = disable dimm 0+1 on channel
-		dimm_channel0_disabled: 2,
-		dimm_channel1_disabled: 2,
-		max_ddr3_freq: 1600,
-		usb_xhci_on_resume: 1,
-		usb2_ports: {
-			/* Length, Enable, OCn#, Location */
-			{ 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
-			  USB_PORT_MINI_PCIE },
-			{ 0x0040, 1, 0,               /* P1: Port A, CN10 */
-			  USB_PORT_BACK_PANEL },
-			{ 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
-			  USB_PORT_INTERNAL },
-			{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
-			  USB_PORT_MINI_PCIE },
-			{ 0x0040, 1, 2,               /* P4: Port B, CN6  */
-			  USB_PORT_BACK_PANEL },
-			{ 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */
-			  USB_PORT_SKIP },
-			{ 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
-			  USB_PORT_FLEX },
-			{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
-			  USB_PORT_SKIP },
-		},
-		usb3_ports: {
-			/* Enable, OCn# */
-			{ 1, 0               }, /* P1; Port A, CN6 */
-			{ 0, USB_OC_PIN_SKIP }, /* P2; */
-			{ 0, USB_OC_PIN_SKIP }, /* P3; */
-			{ 0, USB_OC_PIN_SKIP }, /* P4; */
-		},
-	};
+	struct pei_data pei_data;
 
 	struct romstage_params romstage_params = {
 		.pei_data = &pei_data,
@@ -134,6 +82,9 @@ void mainboard_romstage_entry(unsigned long bist)
 		.bist = bist,
 	};
 
+	/* Fill out PEI data */
+	memset(&pei_data, 0, sizeof(pei_data));
+	mainboard_fill_pei_data(&pei_data);
 	mainboard_fill_spd_data(&pei_data);
 
 	/* Call into the real romstage main with this board's attributes. */