diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S
index 1297296a37..5b10b10118 100644
--- a/src/cpu/x86/64bit/pt.S
+++ b/src/cpu/x86/64bit/pt.S
@@ -20,16 +20,21 @@
 .global PML4E
 .align 4096
 PML4E:
-.quad _GEN_DIR(PDPT)
-
-.align 4096
-PDT: /* identity map 2MiB pages */
-.rept 2048
-.quad _GEN_PAGE(0x200000 * ((. - PDT) >> 3))
+/* For every 512GiB generate a pointer to the corresponding PDPT */
+.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512
+.quad _GEN_DIR(PDPT + 4096 * ((. - PML4E) >> 3)) /* Point to PDPT */
 .endr
 
 .align 4096
-PDPT: /* Point to PDT */
-.rept 4
-.quad _GEN_DIR(PDT + 4096 * ((. - PDPT) >> 3))
+PDT:
+/* For every 2MiB generate a page entry. In one GiB there are 512 pages. */
+.rept 512 * CONFIG_CPU_PT_ROM_MAP_GB
+.quad _GEN_PAGE(0x200000 * ((. - PDT) >> 3)) /* identity map 2MiB page */
+.endr
+
+.align 4096
+PDPT:
+/* For every 1GiB generate a pointer to the corresponding PDT */
+.rept CONFIG_CPU_PT_ROM_MAP_GB
+.quad _GEN_DIR(PDT + 4096 * ((. - PDPT) >> 3)) /* Point to PDT */
 .endr
diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S
index 42cdfb17d0..b1f443301d 100644
--- a/src/cpu/x86/64bit/pt1G.S
+++ b/src/cpu/x86/64bit/pt1G.S
@@ -20,10 +20,14 @@
 .global PML4E
 .align 4096
 PML4E:
-.quad _GEN_DIR(PDPT)
+/* For every 512GiB generate a pointer to the corresponding PDPT */
+.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512
+.quad _GEN_DIR(PDPT + 4096 * ((. - PML4E) >> 3)) /* Point to PDPT */
+.endr
 
 .align 4096
-PDPT: /* identity map 1GiB pages * 512 */
-.rept 512
-.quad _GEN_PAGE(0x40000000 * ((. - PDPT) >> 3))
+PDPT:
+/* For every 1GiB generate a page entry */
+.rept CONFIG_CPU_PT_ROM_MAP_GB
+.quad _GEN_PAGE(0x40000000 * ((. - PDPT) >> 3)) /* identity map 1GiB page */
 .endr
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 828c0f9ce2..15c884e1e8 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -159,6 +159,15 @@ config NEED_SMALL_2MB_PAGE_TABLES
 	  Select this option from boards/SoCs that do not support the Page1GB
 	  CPUID feature (CPUID.80000001H:EDX.bit26).
 
+config CPU_PT_ROM_MAP_GB
+	int
+	default 4 if NEED_SMALL_2MB_PAGE_TABLES
+	default 512
+	help
+	  GiB of the lower address space to identity map when using x86_64
+	  page tables in ROM. Higher values require more space in SPI flash.
+	  SoC can overwrite the value if necessary.
+
 config SMM_ASEG
 	bool
 	default n