From f3adc74e447fc2c93531b7992a5faeb51a531cd9 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 20 Dec 2024 09:32:26 +0530 Subject: [PATCH] mb/google/fatcat: Keep GSPIx interface default PCI BUG=b:377595986 TEST=Able to see 0x12.6 device is visible using `lspci`. Change-Id: Ia3348f78614e61259333ccf2babf20eaf4666a0e Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/85686 Tested-by: build bot (Jenkins) Reviewed-by: YH Lin --- .../google/fatcat/variants/baseboard/fatcat/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index f3a0a65ba5..b9dcbbdf64 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -51,6 +51,12 @@ chip soc/intel/pantherlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI0A] = PchSerialIoPci, + }" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"