From f373faa9c8bc718300b6a15b89c7f7ba2a280fca Mon Sep 17 00:00:00 2001 From: John Su Date: Thu, 21 Aug 2025 16:43:13 +0800 Subject: [PATCH] mb/google/trulo/var/uldrenite: Add fw_config probe for storage Add FW Config probe for uldrenite14 storage. BUG=b:437006063 TEST=emerge-nissa coreboot Change-Id: I744a4e32702175f9c42c884bc76c69a968e74678 Signed-off-by: John Su Reviewed-on: https://review.coreboot.org/c/coreboot/+/88877 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Dtrain Hsu --- .../brya/variants/uldrenite/overridetree.cb | 15 ++++++++- .../google/brya/variants/uldrenite/variant.c | 32 +++++++++++++++++++ 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index 6dc7d4218f..8b9f69ab10 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -19,6 +19,12 @@ fw_config option ISH_DISABLE 0 option ISH_ENABLE 1 end + field STORAGE 30 31 + option STORAGE_EMMC 0 + option STORAGE_NVME 1 + option STORAGE_UFS 2 + option STORAGE_UNKNOWN 3 + end end chip soc/intel/alderlake @@ -500,7 +506,14 @@ chip soc/intel/alderlake device ref shared_sram on end device ref heci1 on end device ref pmc hidden end - device ref emmc on end + device ref emmc on + probe STORAGE STORAGE_EMMC + probe STORAGE STORAGE_UNKNOWN + end + device ref ufs on + probe STORAGE STORAGE_UFS + probe STORAGE STORAGE_UNKNOWN + end device ref uart0 on end device ref pch_espi on chip ec/google/chromeec diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c index a7927eb0d3..0cc6b3972f 100644 --- a/src/mainboard/google/brya/variants/uldrenite/variant.c +++ b/src/mainboard/google/brya/variants/uldrenite/variant.c @@ -86,6 +86,33 @@ static const struct pad_config ish_uart1_disable_pads[] = { PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG), }; +static const struct pad_config emmc_disable_pads[] = { + /* I7 : EMMC_CMD */ + PAD_NC(GPP_I7, NONE), + /* I8 : EMMC_D0 */ + PAD_NC(GPP_I8, NONE), + /* I9 : EMMC_D1 */ + PAD_NC(GPP_I9, NONE), + /* I10 : EMMC_D2 */ + PAD_NC(GPP_I10, NONE), + /* I11 : EMMC_D3 */ + PAD_NC(GPP_I11, NONE), + /* I12 : EMMC_D4 */ + PAD_NC(GPP_I12, NONE), + /* I13 : EMMC_D5 */ + PAD_NC(GPP_I13, NONE), + /* I14 : EMMC_D6 */ + PAD_NC(GPP_I14, NONE), + /* I15 : EMMC_D7 */ + PAD_NC(GPP_I15, NONE), + /* I16 : EMMC_RCLK */ + PAD_NC(GPP_I16, NONE), + /* I17 : EMMC_CLK */ + PAD_NC(GPP_I17, NONE), + /* I18 : EMMC_RST_L */ + PAD_NC(GPP_I18, NONE), +}; + void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { uint32_t board_version = board_id(); @@ -100,6 +127,11 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) gpio_padbased_override(padbased_table, lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); } + if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) { + printk(BIOS_INFO, "Disable eMMC GPIO pins.\n"); + gpio_padbased_override(padbased_table, emmc_disable_pads, + ARRAY_SIZE(emmc_disable_pads)); + } /* b/415605630: Support different ISH UART mappings according the board id */ if (board_version < 2) {