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UPSTREAM: google/pyro: Tune i2c frequency to 400 Khz

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tune i2c devices clk for pyro:
I2C0: audio da7219
I2C2: TPM H1
I2C3: wacom touchscreen
I2C4: elan touchpad

BUG=chrome-os-partner:58881
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: If3c92ed260277c27a94d2fcf7883e9441519e40e
Reviewed-on: https://chromium-review.googlesource.com/410106
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kevin Chiu 2016-11-09 09:52:55 +08:00 • committed by chrome-bot
commit f36d8baa1c
1 changed files with 45 additions and 2 deletions
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47
src/mainboard/google/reef/variants/pyro/devicetree.cb
View file

@ -66,8 +66,51 @@ chip soc/intel/apollolake
register "gpe0_dw2" = "PMC_GPE_N_63_32"
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
# Enable I2C2 bus early for TPM access
register "i2c[2].early_init" = "1"
# Limit I2C0 Audio codec da7219 speed to 400kHz with manually tuned values.
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 0xd0,
.scl_hcnt = 0x68,
.sda_hold = 0x27,
}
}"
# Enable I2C2 bus early for TPM access and configure as 400kHz
# with manually tuned values.
register "i2c[2]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 0xd0,
.scl_hcnt = 0x68,
.sda_hold = 0x27,
}
}"
# Limit I2C3 WACOM touchscreen speed to 400kHz with manually tuned values.
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 0xd0,
.scl_hcnt = 0x68,
.sda_hold = 0x27,
}
}"
# Limit trackpad speed to 400kHz with manually tuned values.
register "i2c[4]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 0xd0,
.scl_hcnt = 0x68,
.sda_hold = 0x27,
}
}"
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"