This commit updates the Geode LX GLCP delay control setup from the v2 way to the v3 way.

This resolves problems with terminated DRAM modules.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Roland G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/amd/db800/romstage.c

@@ -44,8 +44,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 }
 
 #define ManualConf 0		/* Do automatic strapped PLL config */
-#define PLLMSRhi 0x00001490	/* Manual settings for the PLL */
-#define PLLMSRlo 0x02000030
+#define PLLMSRhi 0x000005DD	/* Manual settings for the PLL */
+#define PLLMSRlo 0x00DE60EE
 #define DIMM0 0xA0
 #define DIMM1 0xA2
 
@@ -88,7 +88,7 @@ void main(unsigned long bist)
 
 	pll_reset(ManualConf);
 
-	cpuRegInit();
+	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
 	sdram_initialize(1, memctrl);
 

src/mainboard/amd/norwich/romstage.c

@@ -19,6 +19,7 @@
  */
 
 #include <stdint.h>
+#include <stdlib.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
@@ -88,7 +89,7 @@ void main(unsigned long bist)
 
 	pll_reset(ManualConf);
 
-	cpuRegInit();
+	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
 	sdram_initialize(1, memctrl);
 

src/mainboard/artecgroup/dbe61/romstage.c

@@ -109,7 +109,7 @@ void main(unsigned long bist)
 
 	pll_reset(ManualConf);
 
-	cpuRegInit();
+	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
 	sdram_initialize(1, memctrl);
 

src/mainboard/digitallogic/msm800sev/romstage.c

@@ -1,4 +1,5 @@
 #include <stdint.h>
+#include <stdlib.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
@@ -69,7 +70,7 @@ void main(unsigned long bist)
 
 	pll_reset(ManualConf);
 
-	cpuRegInit();
+	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
 	sdram_initialize(1, memctrl);
 

src/mainboard/iei/pcisa-lx-800-r10/romstage.c

@@ -19,6 +19,7 @@
  */
 
 #include <stdint.h>
+#include <stdlib.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
@@ -92,7 +93,7 @@ void main(unsigned long bist)
 
 	pll_reset(ManualConf);
 
-	cpuRegInit();
+	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
 	sdram_initialize(1, memctrl);
 

src/mainboard/lippert/roadrunner-lx/romstage.c

@@ -122,7 +122,7 @@ void main(unsigned long bist)
 
 	pll_reset(ManualConf);
 
-	cpuRegInit();
+	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
 	sdram_initialize(1, memctrl);
 

src/mainboard/lippert/spacerunner-lx/romstage.c

@@ -184,7 +184,7 @@ void main(unsigned long bist)
 
 	pll_reset(ManualConf);
 
-	cpuRegInit();
+	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
 	/* bit1 = on-board IDE is slave, bit0 = Spread Spectrum */
 	if ((err = smc_send_config(SMC_CONFIG))) {

src/mainboard/pcengines/alix1c/romstage.c

@@ -18,6 +18,7 @@
  */
 
 #include <stdint.h>
+#include <stdlib.h>
 #include <spd.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -148,7 +149,7 @@ void main(unsigned long bist)
 
 	pll_reset(ManualConf);
 
-	cpuRegInit();
+	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
 	sdram_initialize(1, memctrl);
 

src/mainboard/traverse/geos/romstage.c

@@ -88,7 +88,7 @@ void main(unsigned long bist)
 
 	pll_reset(ManualConf);
 
-	cpuRegInit();
+	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
 	sdram_initialize(1, memctrl);
 

src/mainboard/winent/pl6064/romstage.c

@@ -90,7 +90,7 @@ void main(unsigned long bist)
 
 	pll_reset(ManualConf);
 
-	cpuRegInit();
+	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
 	sdram_initialize(1, memctrl);