From f326097fdaa5744571a4b0a32f8eb7ca4d65991d Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 25 Jul 2016 11:29:59 -0600 Subject: [PATCH] rockchip/rk3399: Halt if we get an invalid odt or drv value When we were pushing the updated sdram.c to coreboot.org, the compiler there found that we were not initializing vref_value_dq in all code possible code paths. This patch updates those code paths to halt the system. Branch=none Bug=none Test=Built with coreboot.org toolchain and verified that the compile errors were gone. Change-Id: I0ad4207dc976236d64b6cdda58d10bcfbe1fde11 Signed-off-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/362726 Reviewed-by: Julius Werner --- src/soc/rockchip/rk3399/sdram.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 2264cb9d82..a237a80c7b 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -346,6 +346,8 @@ static void phy_io_config(u32 channel, case PHY_DRV_ODT_60: vref_value_dq = 0x36; break; + default: + die("Halting: Invalid ODT value.\n"); } } else if (drv_value == PHY_DRV_ODT_40) { switch (odt_value) { @@ -358,6 +360,8 @@ static void phy_io_config(u32 channel, case PHY_DRV_ODT_60: vref_value_dq = 0x31; break; + default: + die("Halting: Invalid ODT value.\n"); } } else if (drv_value == PHY_DRV_ODT_34_3) { switch (odt_value) { @@ -370,7 +374,11 @@ static void phy_io_config(u32 channel, case PHY_DRV_ODT_60: vref_value_dq = 0x2e; break; + default: + die("Halting: Invalid ODT value.\n"); } + } else { + die("Halting: Invalid DRV value.\n"); } } else { vref_mode_dq = 0x2; /* LPDDR3 */