erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

ipq8064: Configure storm bootblock to run

Browse source 
This adds necessary configuration options to enable bootblock on Storm
to read the rombase image from the SPI flash.

BUG=chrome-os-partner:27784
TEST=manual
   . after this change is applied, the AP148 boots coreboot from the
     Spansion SPI flash device:

   coreboot-4.0 Thu May  1 14:25:34 PDT 2014 starting...
   Exception handlers installed.
   SF: Detected S25FL128S_256K with page size 10000, total 2000000
   CBFS: loading stage fallback/romstage @ 0x40608000 (7788 bytes), entry @ 0x40608001
   coreboot-4.0 Thu May  1 14:25:34 PDT 2014 booting...
   Exception handlers installed.
...

Original-Change-Id: I9d5e10d6e9f5b60bad5ea71003ea53d8c84ae188
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197801
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 73d72df228)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I509e6da15559c790f129d457d6e463ef90a5dc67
Reviewed-on: http://review.coreboot.org/7995
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Vadim Bendebury 2014-04-30 14:09:36 -07:00 • committed by Kyösti Mälkki
commit f3254348a1
1 changed files with 19 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

21
src/soc/qualcomm/ipq806x/Kconfig
View file

@ -17,11 +17,11 @@ config BOOTBLOCK_ROM_OFFSET
config CBFS_HEADER_ROM_OFFSET
hex "offset of master CBFS header in ROM"
default 0x224000
default 0x228000
config CBFS_ROM_OFFSET
hex "offset of CBFS data in ROM"
default 0x224080
default 0x228080
config MBN_ENCAPSULATION
depends on USE_BLOBS
@ -41,6 +41,15 @@ config BOOTBLOCK_BASE
hex "256K bytes left for TZBSP"
default 0x40600000
config ROMSTAGE_BASE
hex
default 0x40608000
config RAMSTAGE_BASE
hex
default 0x4060c000
config STACK_TOP
hex
default 0x40600000
@ -49,4 +58,12 @@ config STACK_BOTTOM
hex
default 0x405fc000
config CBFS_CACHE_ADDRESS
hex "memory address to put CBFS cache data"
default 0x405e6000
config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
default 0x00016000
endif